Partial Flash Erase for Low-Power Nonvolatile Memory
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in low-power applications where the energy required for erase operations exceeds the available energy, making it difficult to perform both write and erase operations efficiently, especially with scavenged power supplies.
Innovation Solution
The implementation of partial flash erase operations, which break down the erase process into shorter, energy-efficient cycles, allowing for reliable erasure of nonvolatile memory pages using a scavenged power supply by applying reduced voltage and current for shorter durations, and utilizing energy harvesting techniques to accumulate energy between cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a full flash erase operation is performed, then the memory is completely erased, but the energy consumption increases and the operation time extends
Solution Approach 1:
The patent divides the flash memory into multiple pages and implements incremental erase operations that process one page at a time. Instead of erasing the entire flash memory at once, the system erases individual pages sequentially, allowing the application to use previously erased pages while the next page is being erased. This segmentation reduces the energy required for each erase operation and allows the system to function with partial erasure progress.
Solution Approach 2:
The patent performs preliminary erasure of flash pages before they are needed for data storage. By starting the erasure process in advance and continuing it incrementally, the system ensures that pages are ready for use when needed. The erasure operation is initiated before completion, and subsequent pages are erased in the background, ensuring that energy-consuming operations are distributed over time rather than concentrated in a single high-energy event.
2Reliability
If a full flash erase operation is performed, then the memory is completely erased, but the operation duration increases
Solution Approach 1:
The patent divides the flash memory into multiple pages and implements incremental erase operations that process one page at a time. Instead of erasing the entire flash memory at once, the system erases individual pages sequentially, allowing the application to use previously erased pages while the next page is being erased. This segmentation reduces the time the system is blocked during erase operations.
Solution Approach 2:
The patent enables continuous operation by allowing the application to proceed with data storage and communication using already-erased pages while the erasure operation continues in the background on subsequent pages. This eliminates idle time where the system would be blocked waiting for complete erasure, as the useful action of storing and transmitting data continues uninterrupted alongside the incremental erasure process.
3Adaptability or versatility
If traditional flash memory operations are used, then write and erase functions are available, but energy scavenging is insufficient to meet both requirements
Solution Approach 1:
The patent implements a dynamic memory management system that adapts to the available energy from scavenging. The system monitors energy availability and dynamically adjusts its operations accordingly. When energy is available, the system performs write operations; when energy is scarce, it relies on previously erased pages. The erasure process is dynamically controlled to occur incrementally in the background, allowing the system to maintain both write and erase capabilities within the constraints of energy-scavenged power supply.
Solution Approach 2:
The patent performs preliminary erasure of flash pages before they are needed for data storage. By starting the erasure process in advance and continuing it incrementally, the system ensures that pages are ready for use when needed. This preliminary action allows the system to maintain write capability without requiring high-energy full erase operations at the time of writing, thus adapting to energy-scavenged constraints while preserving both write and erase functionality.
Data Source
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AI summary
The erasing of data stored in a nonvolatile memory is performed using multiple partial erase operations. Each partial erase operation has a time duration that is shorter than the minimum time duration of an erase operation that is needed to reliably erase the data stored in the storage location. However, the sum of the time durations of the multiple partial erase operations is sufficient to reliably erase the data in the storage location. In one example, during a partial erase operation, a voltage is applied to a memory storage transistor to remove some, but not necessarily all, of the charge stored on a charge storage layer of the transistor. Following multiple partial erase operations, sufficient charge is removed from the charge storage layer to ensure reliable data erasure.