Partial-Fractional PLL with FIR Filtering for Lower Phase Noise
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Solution Overview
Problem
Designing a satisfactory phase-locked loop for electronic devices with wireless communications capabilities is challenging due to the difficulty in achieving both flexibility in frequency placement and reduced phase noise.
Innovation Solution
Implementing a partial-fractional phase-locked loop (PLL) with a first-order sigma delta modulator and a finite impulse response filter, which generates a periodic deterministic bitstream and attenuates unwanted noise spurs, thereby improving phase noise performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fully-fractional phase-locked loop is used to achieve flexible frequency placement, then adaptability is improved, but phase noise performance deteriorates
Solution Approach 1:
The patent segments the fractional division ratio into an integer portion and a fractional portion, processing them through different paths. The integer portion is handled by a standard frequency divider while the fractional portion is managed by a sigma-delta modulator with noise shaping, allowing flexible frequency placement while isolating and managing the phase noise contributions from each segment separately
Solution Approach 2:
The patent introduces a sigma-delta modulator as an intermediary component between the reference clock and the frequency divider. This mediator shapes and filters the quantization noise, pushing it out of the band of interest, thereby enabling flexible fractional frequency division while maintaining good phase noise performance in the desired frequency range
2Adaptability or versatility
If the raster is reduced to achieve finer frequency resolution, then adaptability is improved, but noise spurs increase
Solution Approach 1:
The patent employs periodic dithering signals added to the fractional division ratio control word. This periodic action randomizes the quantization errors that would otherwise create deterministic noise spurs, converting them into a more uniform noise spectrum that can be better filtered by the loop filter while maintaining fine frequency resolution
Solution Approach 2:
The patent dynamically changes the parameters of the noise shaping filter and dithering mechanism based on the operating conditions and desired frequency resolution. By adjusting the filter coefficients and dither amplitude, the system optimizes the trade-off between frequency resolution and noise spur levels for different operating points
Data Source
AI summary
An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.