Partial GAA FET Dielectric Separation Length Optimization
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Solution Overview
Problem
Conventional finFETs face challenges in scaling gate lengths due to limited gate control and integration issues with gate-all-around (GAA) FETs, leading to suboptimal performance and increased dynamic power consumption in CMOS systems on chip (SoCs).
Innovation Solution
The implementation of partial GAA FETs with varying dielectric separation region lengths and doped extension region configurations allows for optimized threshold voltage and capacitance management, enabling higher performance and reduced dynamic power consumption in CMOS SoCs by differentiating voltage thresholds and resistance characteristics across FET types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If all partial GAA NW FETs have the same length dielectric separation region, then manufacturing is simplified, but performance optimization across different voltage threshold types is compromised
Solution Approach 1:
The patent applies local quality by assigning different dielectric separation region lengths to different voltage threshold types (HVT, RVT, LVT, SLVT) of partial GAA NW FETs. Each FET type receives a customized dielectric separation length optimized for its specific electrical characteristics, allowing simultaneous optimization of multiple device types within the same CMOS SoC without requiring uniform treatment across all devices.
2Object-generated harmful factors
If GAA gate metal is formed in a narrow vertical region between channel regions, then parasitic capacitance is reduced, but achieving desired threshold voltage becomes difficult
Solution Approach 1:
The patent employs parameter changes by adjusting the dielectric separation region length as a critical parameter to control threshold voltage. By varying this geometric parameter across different FET types (from 0 nm to 10 nm or more), the invention achieves precise threshold voltage control (HVT, RVT, LVT, SLVT) while maintaining the narrow gate metal configuration that minimizes parasitic capacitance.
3Reliability
If fin channel width is narrowed to improve gate control, then short-channel effects are reduced, but gate length scaling performance becomes insufficient
Solution Approach 1:
The patent transitions from conventional finFET geometry to partial gate-all-around nanowire FET structure, representing a dimensional change in the gate configuration. This structural evolution enables the gate to wrap around the nanowire channels in multiple dimensions, providing superior gate control and enabling effective scaling to shorter gate lengths while maintaining reliable potential control in the channel regions.
Data Source
AI summary
A CMOS system on chip including a series of partial gate-all-around field effect transistors. Each partial GAA FET includes a fin having a stack of channel regions, source and drain regions on opposite sides of the fin, a dielectric separation region including a dielectric material between first and second channel regions, a gate stack on the fin, and a pair of sidewall spacers on opposite sides of the gate stack. A portion of the dielectric separation region has a length from an outer edge of the dielectric separation region to an inner edge of a respective sidewall spacer. The length of the portion of the dielectric separation region of one of the partial GAA FETs is different than the length of the portion of the dielectric separation region of another one of the partial GAA FETs.