Partial-Gate Avalanche Switch Layout for Low-Power Inverters
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Solution Overview
Problem
Conventional CMOS-based information processing devices face power management issues due to high integration, leading to excessive power loss and performance limits, with steep-switching devices like tunneling FETs and I-MOS experiencing reliability and instability problems at room temperature.
Innovation Solution
A super-steep switching device utilizing avalanche carrier multiplication phenomenon, where a controlled electric field is applied to generate avalanche carrier multiplication in a semiconductor channel, with a gate electrode overlapping only a portion of the channel, achieving a subthreshold swing (SS) value of 5 mV/dec at room temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CMOS devices are highly integrated to improve processing capability, then productivity increases, but power loss increases excessively
Solution Approach 1:
The patent changes the fundamental switching mechanism parameter from thermionic emission to avalanche carrier multiplication, enabling subthreshold swing values below the conventional 60mV/dec limit. This parameter change allows the device to achieve steep switching with lower power consumption while maintaining high integration benefits
2Loss of energy
If steep-switching devices like tunneling FETs are used to reduce power loss, then energy efficiency improves, but reliability deteriorates due to high operation voltage
Solution Approach 1:
The patent changes the switching mechanism from tunneling-based to avalanche-based carrier multiplication. This allows the device to operate at lower voltages (avoiding hot electron damage) while still achieving sub-60mV/dec subthreshold swing, thus improving both energy efficiency and reliability simultaneously
Solution Approach 2:
The patent uses a simple semiconductor channel structure without requiring complex materials like tunneling FETs or negative capacitance FETs. The avalanche carrier multiplication phenomenon can be achieved in conventional semiconductor materials, making the device more reliable and easier to manufacture
3Speed
If high operation voltage is applied to achieve steep switching, then switching speed improves, but hot electron damage to insulators and interfaces increases
Solution Approach 1:
The patent converts the potentially harmful high electric field effect into a beneficial avalanche carrier multiplication phenomenon. By carefully controlling the electric field to be above the critical field for avalanche multiplication but below the breakdown field, the device achieves fast switching without causing hot electron damage to insulators and interfaces
4Ease of operation
If gate electrode overlaps entire semiconductor channel to improve control, then gate control improves, but avalanche carrier multiplication probability decreases
Solution Approach 1:
The patent segments the gate electrode coverage to overlap only a portion of the semiconductor channel. This segmentation allows the ungated portion to experience higher electric fields that promote avalanche carrier multiplication, while the gated portion provides sufficient gate control, achieving both objectives simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device achieves low SS values and high inverter gain with ideal noise margins through a series connection with a pull-up transistor, enabling stable operation and efficient power management.
Implementation Method 1
a voltage for generating an electric field having an intensity higher than a critical electric field intensity, and lower than a breakdown electric field intensity is applied to the drain electrode, wherein the critical electric field intensity is a minimum electric field intensity at which avalanche carrier multiplication occurs in the first area
Data Source
Figure 1
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Figure 3(a)~3(d)
AI summary
A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1: 0.1 to 0.4.