3D Memory Partial Good Block Read Ramping for Peak Power Control
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Solution Overview
Problem
The challenge of peak power spikes during read operations in partial good blocks of memory devices, particularly in multi-deck architectures, due to defective decks causing excessive current consumption, which can lead to malfunctions and inefficiencies in power management systems.
Innovation Solution
Implementing a trim setting adjustment that slows down the wordline ramping rate in partial good blocks by adjusting the clock delay for the charge pump, reducing the voltage ramping rate during read operations to mitigate peak power spikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If read operations are performed in partial good blocks with defective decks, then data access is enabled in degraded memory regions, but peak power spikes and excessive current consumption occur
Solution Approach 1:
The patent changes the wordline ramping rate parameter by adjusting the charge pump clock delay specifically for partial good blocks. This parameter modification reduces the voltage ramping speed, thereby limiting peak current consumption while still enabling read operations to proceed in degraded memory regions.
Solution Approach 2:
The patent applies different operational characteristics to different memory regions: full good blocks operate with normal read parameters, while partial good blocks use modified parameters (slower wordline ramping). This local differentiation allows data access in degraded regions without subjecting them to the same power-intensive operations as healthy regions.
2Speed
If normal wordline ramping rate is used in partial good blocks, then read operation speed is maintained, but excessive current spikes cause malfunctions
Solution Approach 1:
The patent applies a modified wordline ramping rate specifically to the defective portions (partial good blocks) while leaving normal blocks unaffected. This partial application of the rate-limiting measure targets only the problematic regions, maintaining overall system performance while preventing malfunctions in degraded areas.
3Power
If charge pump clock delay is increased to slow wordline ramping, then peak power is reduced, but read latency increases
Solution Approach 1:
The patent segments the memory system into full good blocks and partial good blocks, applying different read operations to each. Only partial good blocks experience the increased clock delay and associated latency penalty, while normal blocks maintain optimal read performance. This segmentation isolates the time loss to only the necessary degraded regions.
Data Source
AI summary
A system includes a memory device with a three-dimensional (3D) memory array having a plurality of blocks. A processing device is coupled to the memory device and determines that a received read command is directed to a partial good block of the plurality of blocks. The processing device identifies, based on the determining, a trim setting associated with a wordline ramping rate of the partial good block. The processing device causes a voltage applied to wordlines of the partial good block to be ramped at a rate according to the trim setting in preparation to perform a read operation in response to the received read command.