Partial Link Width States for Multilane Interconnects
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Solution Overview
Problem
Current interconnect architectures, such as PCIe, face challenges in achieving optimal link width utilization and power efficiency, leading to increased latency and power consumption due to the need for dynamic link width adjustment mechanisms that can introduce significant downtime and latency during link width configuration.
Innovation Solution
The introduction of a partial L0 (PLO) sub-state allows for partial link activity while other lanes perform electrical idle or configuration, enabling low-latency transitions between power states and dynamic power allocation, thereby reducing power consumption proportionate to bandwidth usage without causing link downtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic link width adjustment is implemented to optimize bandwidth utilization, then link width adaptability is improved, but latency and downtime increase during configuration transitions
Solution Approach 1:
The link is divided into multiple independent lanes that can be configured and transitioned separately. During link width adjustment, only the lanes being reconfigured experience interruption while other lanes continue to transmit data, effectively segmenting the transition process to minimize overall downtime.
Solution Approach 2:
The system performs preliminary actions by establishing a new link width configuration before actually transitioning the lanes. The target link width is pre-configured in the destination device, and lanes are prepared in advance to accept the new configuration, allowing for smoother transitions with reduced downtime.
2Productivity
If full link width is maintained during transitions, then data transmission continuity is improved, but power consumption cannot be reduced proportionate to bandwidth usage
Solution Approach 1:
Different lanes within the link are assigned different operational states - some lanes operate at full capacity while others enter low-power states. This allows the system to maintain data transmission continuity on active lanes while reducing power consumption on inactive lanes, achieving local optimization of both productivity and energy efficiency.
Solution Approach 2:
Instead of requiring all lanes to remain fully operational during transitions, the system allows partial link activity where only the necessary number of lanes maintain full operation. This partial action approach enables power consumption to be reduced proportionate to the actual bandwidth needed, while still maintaining sufficient data transmission capacity.
3Speed
If link width transitions are performed rapidly to reduce latency, then transition speed is improved, but configuration accuracy and stability may be compromised
Solution Approach 1:
The link width transition process incorporates feedback mechanisms where the source device monitors the status of lane transitions and adjusts the configuration process accordingly. This feedback ensures that transitions are completed accurately and stabilizes the new link width configuration, preventing rushed or incorrect transitions while maintaining rapid overall transition speed.
Solution Approach 2:
The system dynamically adjusts the transition process based on real-time conditions. Lane transitions can be performed at different speeds and with different levels of precision depending on the specific requirements of each lane and the overall link state, allowing for optimized transition speed and accuracy that adapts to changing conditions.
Data Source
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Figure 2A~2B
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AI summary
Systems and devices can include an upstream port (240), a downstream port (235), and a multilane link (255) connecting the upstream port (240) to the downstream port (235), the multilane link (255) comprising a first link width. The upstream port (240) or the downstream port (235) can be configured to determine that the downstream port (235) is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port (240) an indication of a last data block for the first link width across one or more lanes of the multilane link (255); cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.