Partial Loop-Unrolling SAR ADC for Fast Low-Power SerDes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed analog to digital converters (ADCs) in serializer-deserializer (SerDes) transceivers face challenges in integration due to high power consumption and area occupation, which complicates their implementation, especially in gigabit rate links.
Innovation Solution
A partial loop-unrolling successive approximation register (SAR) ADC design that uses dedicated comparators for most significant bits and a single comparator for least significant bits, along with calibration of comparator offset voltages to minimize dead zones and conversion errors, optimizing power consumption, area, and conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed ADC is integrated in SerDes, then conversion speed is improved, but power consumption increases
Solution Approach 1:
The ADC conversion process is segmented into two distinct phases: a calibration phase for comparator offset correction and a normal conversion phase for signal digitization. This segmentation allows the system to spend minimal time on calibration (not affecting overall conversion speed) while eliminating dead zone errors that would otherwise require larger safety margins in conversion timing, thereby maintaining high conversion speed without proportionally increasing power consumption.
Solution Approach 2:
Comparator offset calibration is performed as a preliminary action before normal conversions. The calibration process pre-corrects comparator offset voltages by determining calibration values that compensate for dead zones. This preliminary correction ensures that subsequent normal conversions proceed without dead zone interruptions, maintaining high conversion speed while the calibration overhead is minimal and can be performed during idle periods or startup.
2Measurement precision
If comparator offset calibration is performed to remove dead zones, then conversion precision is improved, but conversion speed may be reduced
Solution Approach 1:
The calibration process is implemented as a periodic action rather than a continuous process. Calibration is performed at specific intervals (e.g., during startup, after power-on, or during idle periods) to correct comparator offsets. Between calibration periods, the ADC operates at full speed without calibration overhead. This periodic approach maintains high conversion precision by regularly eliminating dead zone effects while preserving conversion speed during the majority of operation time.
Solution Approach 2:
The calibration mechanism uses the ADC's own internal resources and existing circuitry to perform self-calibration. The calibration process leverages the existing comparator infrastructure and conversion logic to determine calibration values without requiring external calibration equipment or additional complex circuitry. This self-service approach minimizes the overhead of calibration while achieving precise dead zone compensation, thereby maintaining both conversion precision and speed.
3Measurement precision
If dedicated comparators are used for MSBs, then conversion accuracy is improved, but area occupation increases
Solution Approach 1:
The calibration and conversion functions are merged into a unified process. The same comparator infrastructure used for normal signal conversion is also used for calibration purposes. During calibration, the comparators evaluate calibration signals to determine offset correction values; during normal operation, they perform signal digitization. This merging eliminates the need for separate dedicated calibration comparators, reducing area occupation while maintaining conversion accuracy through the shared comparator resources.
Solution Approach 2:
The comparators are designed with multi-functionality to serve both calibration and normal conversion tasks. The comparator circuitry can be configured to evaluate different input signals (calibration signals or analog input signals) and perform different functions (determining calibration values or conversion results). This universal design allows the ADC to achieve high conversion accuracy through proper calibration while using the same physical comparators for both purposes, thereby minimizing area occupation.
Data Source
AI summary
A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.