Partial Loop-Unrolled SAR ADC for High-Speed Low-Power Conversion
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Solution Overview
Problem
High-speed analog to digital converters (ADCs) in serializer-deserializer (SerDes) transceivers face challenges in integration due to high power consumption and area occupation, which complicates their implementation, especially in gigabit rate links.
Innovation Solution
A partial loop-unrolling successive approximation register (SAR) ADC design that uses dedicated comparators for most significant bits and a single comparator for least significant bits, with calibration of comparator offset voltages to minimize dead zones and conversion errors, allowing for efficient power consumption and area usage while maintaining high conversion speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional high-speed ADC designs are used, then conversion speed is improved, but power consumption and area occupation increase
Solution Approach 1:
The ADC conversion process is segmented into two distinct phases: a calibration phase that performs offset calibration of comparators, and a conversion phase that performs actual analog-to-digital conversion. This segmentation allows the system to optimize power consumption by performing calibration only when needed, rather than continuously during operation.
Solution Approach 2:
The comparator offset calibration is performed as a preliminary action before the actual conversion process. By pre-calibrating the comparators to eliminate dead zones and offset errors, the system ensures accurate conversion without needing to perform continuous calibration, thereby reducing overall power consumption while maintaining high conversion speed.
2Speed
If traditional high-speed ADC designs are used, then conversion speed is improved, but area occupation increases
Solution Approach 1:
The ADC architecture is segmented into separate calibration and conversion functional blocks. The calibration block contains the necessary comparators and control logic for offset calibration, while the conversion block handles the actual analog-to-digital conversion. This segmentation allows for optimized area utilization by dedicating specific regions to specific functions.
Solution Approach 2:
By performing comparator offset calibration as a preliminary action before conversion, the system eliminates the need for continuous calibration circuits and control logic during the conversion phase. This reduces the overall area occupation while maintaining high conversion speed, as the calibration infrastructure is only active when needed.
3Measurement precision
If comparator offset calibration is performed, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The comparator offset calibration is performed periodically or on-demand rather than continuously. The calibration process is triggered based on system requirements, such as after power-up, after temperature changes, or when accuracy is compromised. This periodic calibration approach maintains high conversion accuracy while significantly reducing power consumption compared to continuous calibration.
Solution Approach 2:
The offset calibration is performed as a preliminary action before the conversion process begins. By completing the calibration beforehand, the system ensures accurate measurements without needing to consume additional power during the actual conversion operation, thus improving accuracy while minimizing power consumption during critical conversion phases.
4Measurement precision
If comparator offset calibration is performed, then conversion accuracy is improved, but conversion speed may be reduced
Solution Approach 1:
The ADC operation is segmented into distinct calibration and conversion phases with clear temporal separation. The calibration phase performs offset calibration to improve accuracy, while the conversion phase performs high-speed analog-to-digital conversion. This segmentation ensures that calibration activities do not interfere with conversion speed, as they occur at different times.
Solution Approach 2:
The comparator offset calibration is performed as a preliminary action before the conversion process. By completing all necessary calibration activities beforehand, the system ensures that the conversion phase can proceed at full speed without interruption or delay from calibration operations, thus maintaining high conversion speed while achieving improved accuracy.
Data Source
AI summary
A receiver system that includes an ADC for converting analog values to digital representations. A digital representation is a sum of discrete values some of which are non-binary scaled and the other are binary scaled. The ADC includes dedicated comparators to determine whether to add or to subtract the non-binary scaled values. A comparator is used to determine whether to add or to subtract the binary scaled values. The ADC further calibrates offset voltages of the comparators to substantially remove dead zone and conversion errors, without compromising the conversion speed. The calibration can be performed both in foreground and background.