Partial Memory Cell Verification for EEPROM
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Solution Overview
Problem
The existing EEPROM verification process is time-consuming and energy-intensive as it requires verifying each memory cell individually, which is inefficient and costly, especially when dealing with memory cells located near structure irregularities or asymmetries in the array.
Innovation Solution
A memory device that verifies only a subset of memory cells, using statistical correction to ensure accuracy, where the subset includes memory cells adjacent to structure irregularities, and adjusts verify levels based on the subset size to compensate for the reduced verification scope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full verification of all memory cells is performed, then verification accuracy is improved, but verification time and energy consumption increase significantly
Solution Approach 1:
The patent applies partial verification by selecting only a subset of memory cells for verification instead of verifying all cells. The selection is based on identifying cells adjacent to structure irregularities or asymmetries in the array, which are more likely to have programming or erasing issues. This partial action approach maintains verification accuracy for critical cells while significantly reducing verification time and energy consumption compared to full verification of all cells.
2Measurement precision
If full verification of all memory cells is performed, then verification accuracy is improved, but energy consumption increases significantly
Solution Approach 1:
The patent reduces energy consumption by performing verification only on a selected subset of memory cells rather than all cells. The subset identification focuses on cells adjacent to structure irregularities or asymmetries, which are the most critical for verification. This partial verification approach maintains sufficient verification accuracy while dramatically reducing the energy required for the verification process compared to full verification.
3Productivity
If subset verification is performed instead of full verification, then verification time is reduced, but verification coverage decreases
Solution Approach 1:
The patent applies local quality by differentiating between different memory cells based on their location and characteristics. Instead of uniform verification of all cells, the system identifies and prioritizes verification of cells adjacent to structure irregularities or asymmetries in the array. This localized approach to verification ensures that the most critical cells are verified while less critical cells are excluded, thereby maintaining verification effectiveness while improving verification speed.
Data Source
AI summary
A memory device comprises a plurality of first and second non-volatile memory cells arranged as an array. Each memory cell stores information. The memory device further comprises an access unit coupled to the array. The access unit stores information in the plurality of first and second non-volatile memory cells. The memory device further comprises a verifying unit coupled to the array. The verifying unit verifies the information stored in a group of the first and second memory cells by verifying only a subset of the group. The subset comprises at least one of the second memory cells.