Partial Memory Mirroring via Target Address Decoders
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Solution Overview
Problem
Full memory mirroring in servers reduces effective physical memory and doubles memory costs, as it requires mirroring all installed DRAM, which is not necessary for all server usage models.
Innovation Solution
Implementing partial memory mirroring, where only a subset of physical DRAM is mirrored, specifically mirroring the OS kernel space or VMM hypervisor space for robustness while leaving application memory space unmirrored, using minimal architectural changes such as target address decoder rules to specify mirrored regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full memory mirroring is implemented, then reliability is improved, but memory cost and memory requirements increase
Solution Approach 1:
The patent segments memory into mirrored and non-mirrored portions, allowing selective mirroring of only critical memory regions (such as kernel space or hypervisor space) rather than all memory. This is achieved through address range decoding that identifies and mirrors only specific memory ranges, reducing the quantity of memory required for mirroring while maintaining reliability for critical operations.
Solution Approach 2:
The patent applies different quality levels of protection to different memory regions. Critical memory regions (kernel space, hypervisor space) receive full mirroring protection for high reliability, while non-critical regions (application space) may have reduced or no mirroring. This local differentiation allows the system to optimize between reliability and memory cost based on the specific needs of each memory region.
2Reliability
If full memory mirroring is implemented, then reliability is improved, but effective physical memory decreases
Solution Approach 1:
By segmenting memory into mirrored and non-mirrored portions, the patent allows the system to maintain full effective physical memory for non-mirrored regions while applying mirroring only to specific critical regions. This segmentation enables the system to avoid the 50% memory loss that would occur with full mirroring, as only a portion of memory is duplicated for redundancy.
Solution Approach 2:
The patent implements partial mirroring rather than complete mirroring of all memory. By applying mirroring to only the extent necessary for critical operations (kernel space, hypervisor space), the system achieves sufficient reliability without the excessive memory consumption that would result from mirroring the entire memory space.
3Quantity of substance
If partial memory mirroring is implemented, then memory cost is reduced, but complexity of memory management increases
Solution Approach 1:
The patent implements self-service mechanisms where the memory controller automatically handles the complexity of partial mirroring management. The address range decoding logic within the memory controller autonomously determines which memory addresses require mirroring based on predefined ranges, eliminating the need for complex software-based memory management and reducing overall system complexity despite the partial mirroring implementation.
4Quantity of substance
If partial memory mirroring is implemented, then memory cost is reduced, but architectural complexity increases
Solution Approach 1:
The patent introduces an intermediary address range decoding mechanism that mediates between the memory controller and the mirrored/non-mirrored memory regions. This decoder acts as an intermediary layer that automatically determines whether a given memory address should be mirrored based on predefined address ranges, thereby managing architectural complexity through a dedicated intermediary component rather than requiring complex coordination across multiple system layers.
Data Source
AI summary
An apparatus and method are described for performing partial memory mirroring operations. For example, one embodiment of a processor comprises: a processor core for generating a read or write transaction having a system memory address; a home agent identified to service the read or write transaction based on the system memory address; one or more target address decoders (TADs) associated with the home agent to determine whether the system memory address is within a mirrored memory region or a non-mirrored memory region, wherein: if the system memory address is within a mirrored memory region, then the one or more TADs identifying multiple mirrored memory channels for the read or write transaction; and if the system memory address is not within a mirrored memory region, then the one or more TADs identifying a single memory channel for the read or write transaction.