Partial Self-Aligned MOL Contacts for Short-Resistant Gate Scaling
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Solution Overview
Problem
Traditional self-aligned contact (SAC) processes face challenges with scaling beyond 7 nm technologies, including gate bending issues and increased production costs, while non-SAC middle-of-line (MOL) designs struggle with gate-to-source/drain shorts and compatibility with active area designs.
Innovation Solution
The development of middle-of-line (MOL) partial self-aligned contact structures, where a combination of first and second spacers surrounds the upper portion of the gates, allowing for fully self-aligned gate contacts and partially self-aligned upper source and drain contacts, without the need for gate recessing, thereby improving contact-to-gate short overlay margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional self-aligned contact (SAC) process is used, then contact alignment is improved, but gate height increases causing gate bending issues
Solution Approach 1:
The gate structure is segmented into multiple metal layers (workfunction-setting metal layer and inner core metal layer) with different functions. The workfunction-setting metal layer is positioned at the lower portion to establish proper gate voltage, while the inner core metal layer is positioned at the upper portion to provide mechanical support and prevent gate bending, thus resolving the contradiction between contact alignment and gate shape stability
Solution Approach 2:
Different portions of the gate structure are assigned different material properties and functions. The lower portion uses workfunction-setting metal for electrical characteristics, while the upper portion uses inner core metal for structural integrity. This local differentiation allows the gate to simultaneously achieve proper contact alignment and resist bending deformations
2Ease of manufacture
If non-SAC middle-of-line (MOL) design is used, then production cost decreases, but gate-to-source/drain shorts occur
Solution Approach 1:
The process utilizes self-aligned spacer formation where spacers are deposited conformally on the gate structure and then anisotropically etched to automatically define the contact regions. This self-aligned approach eliminates the need for complex lithographic alignment steps, maintaining low production costs while preventing gate-to-source/drain shorts through precise spatial separation
Solution Approach 2:
Spacers serve as intermediary structures that physically separate the gate from source/drain regions. These spacers are formed through conformal deposition and anisotropic etching, creating a reliable isolation barrier that prevents shorts while maintaining a simplified manufacturing process compatible with MOL design
3Ease of manufacture
If non-SAC MOL structure is used, then production cost decreases, but compatibility with gate contact over active area design is lost
Solution Approach 1:
The dual-layer gate structure with workfunction-setting metal and inner core metal provides multiple functions: electrical gate control, mechanical support, and compatibility with various contact configurations including gate contact over active area designs. This universal structure can accommodate different device layout requirements while maintaining cost-effective manufacturing
4Productivity
If gate pitch is scaled down, then device density increases, but gate-to-source/drain shorts become more likely
Solution Approach 1:
The solution moves from two-dimensional planar spacing to three-dimensional vertical spacer structures. By forming spacers that extend vertically from the gate bottom to the gate top, the process creates additional spatial separation in the vertical dimension, effectively preventing shorts even when horizontal pitch scaling reduces lateral separation distances
Data Source
AI summary
Partial self-aligned contact structures are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming a gate(s) over the fins, separated from source/drains by first spacers, wherein a lower portion of the gate(s) includes a workfunction-setting metal, and an upper portion of the gate(s) includes a core metal between a metal liner; recessing the metal liner to form divots in the upper portion of the gate(s) in between the first spacers and the core metal; forming second spacers in the divots such that the first spacers and the second spacers surround the core metal in the upper portion of the gate(s); forming lower source/drain contacts in between the first spacers over the source/drains; recessing the lower source/drain contacts to form gaps over the lower source/drain contacts; and forming source/drain caps in the gaps. A semiconductor device is also provided.