Partial N-Type Isolation in CMOS Photodetector Trenches
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Solution Overview
Problem
CMOS image sensors face issues with increased peripheral capacitance and dark current due to shallow trench isolation regions, which affect the fill factor and performance of the pixels.
Innovation Solution
The formation of shallow trench isolation regions with a dielectric structure, where the n-type isolation layer is only partially surrounding the photodetector, reducing capacitance and dark current, and allowing for a wider photodetector and smaller transistors, thereby increasing the pixel fill factor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation regions with n-type isolation layer completely surrounding the photodetector are used, then electrical isolation between pixels is improved, but peripheral capacitance and dark current increase
Solution Approach 1:
The patent applies local quality by making the isolation layer configuration non-uniform: an n-type isolation layer is present on the first sidewall and bottom of the trench adjacent to the photodetector, but deliberately omitted from the second sidewall and opposite bottom portion. This localized differentiation reduces peripheral capacitance and dark current while maintaining necessary electrical isolation, directly resolving the technical contradiction between complete isolation and harmful capacitance effects.
2Reliability
If n-type isolation layer is formed on all sidewalls and bottom of trenches, then pixel electrical isolation is improved, but transistor effective width is reduced
Solution Approach 1:
The patent implements local quality by selectively positioning the n-type isolation layer only on the first sidewall and bottom of the trench that are adjacent to the photodetector, while intentionally leaving the second sidewall and opposite bottom portion without isolation layer. This localized approach maintains electrical isolation where needed while preserving transistor effective width in other areas, thereby resolving the contradiction between complete isolation and transistor width reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces dark current and peripheral capacitance, allowing for a larger photodetector area and wider transistors, enhancing the image sensor's performance and fill factor.
Implementation Method 1
Pixel 100 includes photodetector (PD) 102 that collects charge in response to incident light
Implementation Method 2
can cause higher dark current or point defects due to the p+/n+ diode junction formed by the n-type isolation layer and the p-type charge-to-voltage conversion region
Data Source
AI summary
Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.