Partial Page Sensing in 3D NAND via Floating Bit Lines
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Solution Overview
Problem
Partial page sensing (PPS) in 3D NAND flash memory devices experiences significant delays and high Intraclass Correlation Coefficient (Icc) due to strong bit line-bit line capacitive coupling, leading to slower sensing and reading times, rendering existing PPS operations ineffective.
Innovation Solution
The method involves applying a bit line voltage to selected bit lines while floating unselected bit lines, rather than grounding them, to reduce capacitive coupling and enhance sensing speed in partial page operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If unselected bit lines are grounded during partial page sensing, then capacitive coupling is reduced, but sensing speed decreases and read times increase
Solution Approach 1:
Instead of grounding the unselected bit lines as conventionally done, the patent inverts the approach by floating the unselected bit lines during partial page sensing operations. This inversion eliminates the capacitive coupling path to ground while maintaining signal integrity on selected bit lines, thereby resolving the contradiction between reducing capacitive coupling and maintaining sensing speed
Solution Approach 2:
The patent changes the electrical state parameter of unselected bit lines from grounded (0V) to floating (high impedance state). This parameter change modifies the capacitive coupling characteristics without affecting the selected bit lines, enabling faster sensing by eliminating the harmful capacitive effect while preserving the useful signal paths
2Stability of the object's composition
If unselected bit lines are grounded during partial page sensing, then circuit stability is maintained, but read times increase
Solution Approach 1:
The patent inverts the conventional grounding approach for unselected bit lines during partial page sensing. By floating these bit lines instead of grounding them, the patent achieves faster read times while maintaining circuit stability through controlled impedance management and selective activation of sensing circuits only for the selected partial page
Solution Approach 2:
The patent applies partial action by enabling sensing operations only for the selected partial page while leaving other bit lines in a high-impedance floating state. This selective activation reduces the active capacitive coupling in the circuit, thereby reducing read times without compromising the stability of the overall circuit architecture
3Device complexity
If conventional partial page sensing is used, then device complexity is reduced, but sensing efficiency decreases
Solution Approach 1:
The patent introduces dynamic control of bit line states during partial page sensing operations. By dynamically switching between grounded and floating states based on selection status, the patent achieves faster sensing efficiency without requiring additional hardware complexity, as the same bit line infrastructure is used with improved temporal control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces capacitive coupling, resulting in faster ramp-up and read times, and shorter sensing times for selected partial pages, thereby improving the efficiency of partial page sensing operations.
Implementation Method 1
Partial page sensing (PPS) in 3D NAND flash memory devices experiences significant delays and high Intraclass Correlation Coefficient (Icc) due to strong bit line-bit line capacitive coupling
Data Source
AI summary
A partial page sensing method and system are provided in which, while a bit line voltage (VBLC) is applied to first bit lines of a first partial page of a memory cell array, second bit lines, of a second partial page are floated. The second bit lines of the second partial page are bit lines which are interleaved with the first bit lines of the first partial page. Bit lines associated with one or more additional partial pages may be grounded or floated. A bit line associated with an additional partial page which is adjacent to one of the first bit lines may be floated.