Partial Rank Bank Interleaving for Non-Symmetric DIMMs
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Solution Overview
Problem
Existing information handling systems with non-symmetrically populated DIMMs across DDR channels face inconsistent bandwidth and latency performance due to unequal distribution of memory accesses across interleave groups, leading to inefficient use of DDR channels and suboptimal memory subsystem performance.
Innovation Solution
Implementing a memory interleaving method that allocates each interleave group access to memory locations across all DDR channels, dividing banks and ranks evenly across available DIMMs to ensure consistent performance levels between interleave groups, thereby maximizing bandwidth and minimizing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory interleaving is implemented with non-symmetrically populated DIMMs across DDR channels, then memory capacity is increased, but bandwidth consistency and latency performance deteriorate due to unequal distribution of memory accesses across interleave groups
Solution Approach 1:
The patent applies asymmetry by creating interleave groups that are deliberately unbalanced in terms of the number of DIMMs they contain. Instead of requiring symmetric population across channels, the system allows interleave groups to have different numbers of DIMMs (e.g., first interleave group with fewer DIMMs, second interleave group with more DIMMs) while still achieving consistent performance through careful bank distribution across all groups.
Solution Approach 2:
The patent implements local quality by ensuring that each interleave group, regardless of its size, contains a proportional representation of banks from each DIMM. This means that while the number of DIMMs per interleave group may differ, each group maintains equivalent access patterns and performance characteristics by distributing banks evenly within each group's composition.
2Adaptability or versatility
If conventional memory interleaving is used with non-symmetric DIMM population, then system configuration flexibility is improved, but memory access latency increases due to suboptimal utilization of DDR channels
Solution Approach 1:
The patent applies dynamics by making the interleave group configuration adaptable to different DIMM population scenarios. The system dynamically determines how to distribute DIMMs across interleave groups based on the actual hardware configuration, allowing flexible adaptation to various memory subsystem layouts while maintaining optimal access patterns through proportional bank distribution.
Solution Approach 2:
The patent changes the parameter of interleave group composition from fixed symmetric requirements to flexible asymmetric allocations. By allowing the number of DIMMs per interleave group to vary while maintaining proportional bank representation, the system optimizes memory access latency across different configuration scenarios without being constrained by symmetric population requirements.
3Loss of energy
If DIMMs are non-symmetrically populated across DDR channels, then hardware cost is reduced, but memory subsystem performance deteriorates due to inefficient use of available bandwidth
Solution Approach 1:
The patent enables the memory subsystem to self-optimize its performance by automatically distributing banks across interleave groups in a manner that fully utilizes all available DDR channels. The system inherently balances the workload across all channels regardless of asymmetric DIMM population, allowing cost-effective hardware configurations to achieve optimal performance without requiring additional hardware or complex external intervention.
Data Source
AI summary
An information handling system includes a processor having a plurality of memory channels. The information handling system also includes a plurality of dual inline memory modules non-symmetrically populated on the memory channels. The dual inline memory modules are divided by bank to create a plurality of interleave groups, and each of the interleave groups spans across all of the memory channels of the processor.