Programmable Circuitry Partial Reconfiguration With Bitstream Validation
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Solution Overview
Problem
Dynamic partial configuration of programmable logic devices (PLDs) lacks validation prior to loading configuration bits, leading to potential errors such as improper functioning or permanent damage.
Innovation Solution
Implementing a method that includes a configuration controller, buffer, and error checker to validate configuration bits before loading them into the programmable logic, ensuring the integrity of the configuration data during dynamic partial configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dynamic partial configuration is performed without validation, then configuration speed is improved, but device reliability deteriorates due to potential errors and damage
Solution Approach 1:
The patent applies preliminary action by performing validation of configuration bits before they are loaded into the programmable logic device. The validation circuit checks configuration bits in advance to detect errors such as stuck-at faults, transition faults, and functional faults, preventing erroneous configuration data from being instantiated. This preliminary validation step ensures device reliability while maintaining the speed benefits of dynamic partial configuration.
2Reliability
If validation is performed during dynamic partial configuration, then device reliability is improved, but configuration complexity increases
Solution Approach 1:
The patent introduces an intermediary validation circuit that mediates between the configuration data source and the programmable logic device. This validation circuit acts as a buffer that checks configuration bits for errors before they are loaded, without requiring fundamental changes to the dynamic partial configuration architecture. The intermediary validation layer adds reliability while maintaining relatively simple integration with existing configuration mechanisms.
3Manufacturing precision
If configuration bits are validated before loading, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
The patent applies local quality by performing validation only on the specific configuration bits that are being dynamically reconfigured, rather than validating the entire configuration set. The validation circuit focuses its checking resources on the particular configuration data portion that is currently being loaded into the programmable logic device. This localized validation approach ensures configuration precision while minimizing the time penalty compared to comprehensive validation.
Data Source
AI summary
Partial configuration of programmable circuitry with validation for an integrated circuit is described. An integrated circuit with programmable circuitry is obtained. The programmable circuitry is configured with a first bitstream in a non-dynamic mode of operation, after which the integrated circuit includes a configuration controller coupled to a buffer, an internal configuration access port, and an error checker. A portion of a second bitstream is loaded into the buffer for a dynamic partial configuration mode of operation. The portion of the second bitstream loaded into the buffer is validated with the error checker as being acceptable, after which the portion of the second bitstream is instantiated in the programmable circuitry via the internal configuration access port.