Partial Reconfiguration Debugging with a Fixed Signal Interface
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods of partial reconfiguration in programmable logic devices interfere with real-time debugging, causing severed connections and loss of signal visibility due to changes in the reconfigurable region of logic during partial reconfiguration.
Innovation Solution
Implementing a fixed interface, such as a port, between the reconfigurable and fixed regions of logic that maintains constant connections with an embedded logic analyzer, allowing for real-time monitoring of signal behavior during partial reconfiguration by routing signals through a signal interface that remains unchanged regardless of the logic instantiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If partial reconfiguration is implemented in a programmable logic device, then adaptability and versatility are improved, but connectivity and signal visibility are lost due to severed connections in the reconfigurable region
Solution Approach 1:
The PLD is divided into reconfigurable regions and fixed regions. The reconfigurable regions can be dynamically reconfigured while the fixed regions remain stable and maintain connectivity to external systems. This segmentation allows partial reconfiguration without losing overall system connectivity.
Solution Approach 2:
Fixed regions act as intermediaries between the reconfigurable regions and external computing systems. These fixed regions maintain stable signal paths and connections, serving as mediators that ensure continuous signal visibility even when reconfigurable regions change their logic instantiation.
2Adaptability or versatility
If the reconfigurable region of logic is changed during operation, then adaptability is improved, but debugging capability deteriorates due to loss of signal visibility
Solution Approach 1:
The device is segmented into reconfigurable and fixed regions with distinct functions. The fixed regions maintain stable signal paths that are accessible for debugging, while the reconfigurable regions can change logic instantiation without affecting the debugging capability of the fixed regions.
Solution Approach 2:
The fixed regions maintain continuous signal paths and connectivity throughout the reconfiguration process. This ensures that debugging capabilities remain uninterrupted and continuously available, allowing real-time monitoring and analysis even as the reconfigurable regions change their logic implementation.
3Adaptability or versatility
If conventional reconfiguration methods are used, then device functionality is improved, but device complexity increases due to interrupted debugging processes
Solution Approach 1:
By segmenting the PLD into reconfigurable and fixed regions with clearly defined roles, the system achieves reconfiguration functionality without proportionally increasing debugging complexity. The fixed regions provide stable, predictable signal paths that simplify the debugging process compared to entirely reconfigurable systems.
Data Source
AI summary
Embedded logic is implemented in a partially reconfigurable programmable logic device (PLD), thus allowing debugging of implemented instantiations of logic after partial reconfiguration. Several instantiations of logic are received at the PLD. One instantiation of logic is implemented in a reconfigurable region of logic within the PLD. The instantiation of logic includes a port that provides a constant interface between the reconfigurable region of logic and a fixed region of logic within the PLD. The port may receive signals from probe points implemented within the reconfigurable region of logic. The port may provide the signals to a signal interface implemented within a fixed region of logic. Furthermore, an embedded logic analyzer may be implemented in either the reconfigurable region of logic or the fixed region of logic. The embedded logic analyzer receives signals from the probe points and provides signal visibility to an external computing system.