Partial Reconfiguration Floorplanning With Integrated DRC
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Solution Overview
Problem
Current methods for partial reconfiguration of programmable logic devices (PLDs) require a strict and disparate design methodology, lacking a single environment for managing circuit design effectively.
Innovation Solution
A graphical environment is introduced for circuit design, allowing for the import and processing of logical descriptions, floorplanning to locate static and reconfigurable logic, and performing design rule checks to manage partial reconfiguration implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strict design methodology using disparate tools is used for partial reconfiguration, then the design can be implemented, but the design process becomes complex and difficult to manage
Solution Approach 1:
The patent merges multiple disparate design tools into a single integrated graphical environment that provides unified support for partial reconfiguration design. The system combines floorplanning, design rule checking, and implementation management in one platform, eliminating the need to switch between multiple separate tools and thereby reducing design process complexity while maintaining reliable implementation.
Solution Approach 2:
The graphical environment is designed as a universal platform that performs multiple design functions simultaneously - it can import logical descriptions, perform floorplanning, execute design rule checks, and manage partial reconfiguration implementation all within a single tool. This multi-functional approach replaces the need for multiple specialized tools, simplifying the overall design workflow.
2Manufacturing precision
If manual floorplanning and design rule checking are performed, then design control is maintained, but the design process time increases
Solution Approach 1:
The system implements automated design rule checking that performs compliance verification without requiring manual intervention. The graphical environment automatically checks design rules during the floorplanning and implementation processes, providing self-service validation that ensures design rule compliance while significantly reducing the time compared to manual checking methods.
Solution Approach 2:
The patent replaces manual mechanical processes of design rule checking with automated computational methods. The system uses algorithmic design rule checking to validate designs, substituting the time-consuming manual review process with automated software-based verification that maintains precision while reducing process time.
3Adaptability or versatility
If separate tools are used for each design step, then specialized functionality is available, but the overall design flow becomes fragmented and less efficient
Solution Approach 1:
The patent combines multiple specialized design tools into a single integrated graphical environment that maintains the specialized functionality of each tool while improving overall design flow efficiency. The unified platform provides seamless integration between floorplanning, design rule checking, and implementation management, eliminating the fragmentation caused by using separate tools for each design step.
Data Source
AI summary
Method, apparatus, and computer readable medium for circuit design for a programmable device is described. In one example, a logical description of a circuit design having static logic and reconfigurable logic is imported into a graphical environment. The circuit design is processed in the graphical environment. In particular, the logical description is floorplanned to locate the static logic and the reconfigurable logic in a floorplan of the programmable device. At least one design rule check (DRC) is performed. A partial reconfiguration implementation of the circuit design is then managed for the programmable device.