Partial Reconfiguration Interface Net Exclusion for Logic Optimization

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Solution Overview

Problem

Conventional electronic design automation (EDA) systems refrain from performing logical and physical optimizations during partial reconfiguration design flows for integrated circuits (ICs) to preserve the integrity of interfaces between static and reconfigurable modules, resulting in lower Quality of Results (QOR) compared to default design flows.

Innovation Solution

A method and system for performing logical and physical optimizations in a partial reconfiguration design flow that preserves the functionality and integrity of interfaces between static circuitry and reconfigurable modules by excluding interface nets from processing, allowing optimizations to be applied to static and reconfigurable circuitry separately without modifying the interface functionality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If logical and physical optimizations are performed during partial reconfiguration design flow, then Quality of Results (QOR) is improved, but interface integrity between static and reconfigurable modules is compromised

Engineering Contradiction:
ImproveQuality of ResultsVSAvoidinterface integrity
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The circuit design is segmented into static circuitry and reconfigurable modules with clearly defined boundaries. The interface nets connecting these segments are identified and excluded from optimization processing, allowing optimizations to be applied independently to each segment without affecting interface integrity. This segmentation enables parallel optimization of internal circuitry while preserving external interface functionality.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Interface nets are extracted and separated from the optimization process. By identifying and removing interface nets from the set of circuits subject to logical and physical optimizations, the system allows aggressive optimization of internal circuitry while ensuring that interface connections remain untouched and preserve their intended functionality across module boundaries.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If interface nets are included in optimization processing, then resource utilization is improved, but interface functionality is modified

Engineering Contradiction:
Improveresource utilizationVSAvoidinterface functionality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Interface nets are extracted and separated from the optimization process. By identifying and removing interface nets from the set of circuits subject to logical and physical optimizations, the system allows aggressive optimization of internal circuitry while ensuring that interface connections remain untouched and preserve their intended functionality across module boundaries.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Different optimization strategies are applied to different parts of the circuit. Internal circuitry within reconfigurable modules and static circuitry undergo full optimization for resource utilization, while interface nets are excluded from optimization to maintain their specific functionality. This local differentiation of optimization intensity resolves the contradiction between resource utilization and interface functionality preservation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10303648B1Logical and physical optimizations for partial reconfiguration design flow
Publication Date: 2019.05.28 XILINX INC
  • US10303648B1 patent drawing
  • US10303648B1 patent drawing
  • US10303648B1 patent drawing

AI summary

Implementing a partial reconfiguration design flow can include determining an interface net connecting static circuitry and a first reconfigurable module of a circuit design, performing, using a processor, a logical optimization on first circuitry of the static circuitry that is entirely external to the first reconfigurable module and on second circuitry entirely within the reconfigurable module, and excluding the interface net from processing using the logical optimization.