Partial Refresh Memory Controller for Von Neumann Bottleneck
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Solution Overview
Problem
The von Neumann bottleneck in conventional computer architecture limits processing speeds due to throughput limitations in data transfer from memory to processors, particularly in memory-intensive tasks like neural networks and database operations, and existing systems struggle to keep up with the rapid growth of large data volumes and processing requirements.
Innovation Solution
The development of hardware chips with distributed processor subunits and dedicated memory banks, allowing for parallel execution of instructions and optimized data access through dedicated buses and software-configurable refresh controllers, enabling efficient memory management and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional computer architecture with separate memory and processor is used, then data storage capacity is improved, but processing speed deteriorates due to von Neumann bottleneck
Solution Approach 1:
The patent merges memory and processing functions into a single integrated circuit substrate. Memory cells are directly coupled to processing elements on the same chip, eliminating the von Neumann bottleneck by allowing simultaneous data storage and computation without external bus transfers.
Solution Approach 2:
The patent transitions from traditional hierarchical memory architecture to a two-dimensional array of memory cells with direct processing element access. This spatial reorganization allows multiple processing elements to access different memory cells simultaneously, increasing throughput while maintaining large storage capacity.
2Reliability
If memory refresh operations are performed frequently to maintain data integrity, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements selective refresh where only portions of the memory array that contain valid data requiring maintenance are refreshed, rather than performing full array refresh operations. This reduces power consumption while maintaining data integrity for actively used memory regions.
Solution Approach 2:
The patent uses refresh controllers that monitor memory cell states and perform refresh operations proactively before data loss occurs. By predicting which memory regions need refresh based on access patterns and timing, the system maintains reliability while minimizing unnecessary refresh operations and power consumption.
3Quantity of substance
If memory array size is increased to handle large data sets, then data handling capability is improved, but access time increases
Solution Approach 1:
The patent divides the large memory array into multiple smaller memory banks or segments that can be accessed independently. Processing elements can access different segments simultaneously, maintaining low access times even as total memory capacity increases to handle large data sets.
Solution Approach 2:
The patent optimizes the local access characteristics of memory segments by placing frequently accessed data closer to processing elements and organizing memory geometry to minimize access paths. This ensures that while total capacity is large, the access time for relevant data remains short.
Data Source
AI summary
A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.