Clock Data Recovery Using Partial-Response DFE for Jittered Links
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Solution Overview
Problem
Current data exchange technologies face inefficiencies in high-speed serial links, particularly in clock data recovery, where existing systems struggle to maintain accurate phase locking and efficiently handle signal jitter and off-center sampling, especially at high data transfer rates like 17 Gbps.
Innovation Solution
The proposed clock data recovery system employs 2-tap partial response equalization with baud rate clock recovery, utilizing a 2-tap or 1-tap partial response decision feedback equalization and includes a high-pass filter, clocked-data comparators, and error comparators to adapt phase locking at h0=h1+h2, enhancing signal processing and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional clock data recovery methods are used in high-speed serial links, then the system can operate at high data transfer rates, but phase locking accuracy deteriorates and signal jitter increases
Solution Approach 1:
The patent implements dynamic phase adjustment mechanisms that continuously adapt the sampling phase based on detected signal characteristics. The equalization filter dynamically adjusts its coefficients to compensate for channel variations, and the phase detector continuously refines the sampling timing to maintain optimal phase locking despite high-speed operation and signal jitter
Solution Approach 2:
The system employs feedback loops where the output of the equalization filter is fed back to adjust the sampling phase and equalization coefficients. The phase detector uses feedback from error signals to continuously correct phase deviations, ensuring accurate phase locking is maintained even at high data transfer rates where jitter and off-center sampling occur
2Productivity
If conventional equalization methods are used, then the system structure remains simple, but signal processing efficiency deteriorates at high speeds
Solution Approach 1:
The equalization process is segmented into multiple taps, where each tap processes a different portion of the signal history. This multi-tap structure allows the system to handle complex high-speed signal characteristics by dividing the equalization task into manageable segments, improving signal processing efficiency without requiring a completely complex monolithic structure
Solution Approach 2:
The system dynamically changes equalization parameters (coefficients) based on detected signal conditions. By adapting the equalization coefficients in real-time based on channel characteristics and signal quality, the system achieves high signal processing efficiency without requiring a fixed complex structure, as the same structure can be optimized through parameter adjustment
3Measurement precision
If standard comparator designs are used, then the device complexity remains low, but error detection accuracy deteriorates due to signal jitter and off-center sampling
Solution Approach 1:
The equalization filter performs preliminary signal conditioning before the comparators perform error detection. By pre-processing the signal to reduce jitter and correct for off-center sampling effects, the comparators receive cleaner, more centered signals that are easier to detect accurately, improving error detection accuracy without requiring overly complex comparator circuits
Data Source
AI summary
A clock data recovery system is described. It includes a high pass filter for transmitting a filtered data signal in response to receiving an input data signal; an adder for summing the filtered data signal with a feedback signal, wherein the adder produces a summed input signal; a plurality of clocked data comparators for receiving the summed input signal, wherein the clocked data comparators determine an input data bit value; a plurality of clocked error comparators for receiving an error signal associated with clock recovery and DFE tap adaption; an equalization and adaptation logic for selecting an error sample such that a phase associated with the error sample is locked at h0=h1+h2; and a phase mixer for transmitting a delay in response to receiving the phase and the delay is transmitted to the clocked-data comparators and the clocked-error comparators.