Multi-Phase Partial Response Equalizer for High-Rate ISI Mitigation
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Solution Overview
Problem
Conventional partial response equalizers face challenges in operating at higher data rates due to the limitations imposed by the longest feedback path delay, which restricts their ability to effectively mitigate dispersion-type inter-symbol interference (ISI) at faster signaling rates.
Innovation Solution
The implementation of a multi-data rate partial response equalizer that employs a time borrowing technique, allowing for increased time for signal propagation between sampled bits without altering the clock signal periods, thereby reducing timing constraints and enabling operation at higher data rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional partial response equalizer is used, then dispersion-type ISI can be mitigated, but the operating data rate is limited by the longest feedback path delay
Solution Approach 1:
The feedback path is segmented into multiple parallel paths with different delay elements. Instead of a single long feedback path, the circuit divides the feedback into multiple shorter paths (e.g., one-unit-interval and two-unit-interval paths) that can be processed in parallel, reducing the critical path delay and enabling higher data rates.
Solution Approach 2:
The equalizer transitions from a single-data-rate architecture to a multi-data-rate architecture by introducing parallel processing paths. This dimensional change in the time domain allows multiple feedback operations to occur simultaneously at different rates, effectively reducing the perceived feedback delay for high-speed operation.
2Productivity
If clock rate is increased to achieve higher data rates, then productivity improves, but the timing constraints become more difficult to meet due to fixed feedback path delays
Solution Approach 1:
The equalizer employs dynamic timing adjustment by using multi-data-rate sampling where different feedback paths operate at different rates relative to the main clock. This dynamic approach allows the system to adapt timing relationships to meet setup and hold requirements even at increased clock rates, maintaining reliability while improving productivity.
Solution Approach 2:
The system changes the timing parameters of the feedback paths by introducing variable delay elements that can be adjusted based on the operating clock rate. This allows the feedback path delays to be optimized for different data rates, ensuring timing constraints are met across a wide range of operating conditions.
Data Source
AI summary
A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal.