Partial Retention Synthesis for Power-Down Register Optimization
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Solution Overview
Problem
In integrated circuit design, minimizing power consumption is challenging due to the need for retention registers that draw more power and occupy larger areas, especially in mobile electronics where battery-driven devices require efficient power management, and manually selecting non-retention registers is time-consuming and error-prone.
Innovation Solution
The method analyzes circuit designs, functional test sequences, and power specifications to automatically identify registers that do not need retention, using symbolic simulation to determine retention status and reduce the number of retention registers, thereby optimizing power consumption and chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full retention is implemented to preserve all register values during power-down, then circuit behavior reliability is improved, but power consumption and chip area increase
Solution Approach 1:
The patent extracts and identifies the minimal subset of registers that actually require retention by analyzing data flow and dependency relationships. Instead of retaining all register values, the system selectively retains only those registers whose values are needed after power-up, thereby reducing power consumption while maintaining circuit reliability for critical data preservation.
Solution Approach 2:
The patent applies different retention strategies to different registers based on their specific data flow characteristics and dependency relationships. Each register is individually analyzed to determine whether it requires retention, partial retention, or no retention, allowing optimized power consumption for each local region of the circuit rather than uniform full retention across all registers.
2Reliability
If full retention is implemented to preserve all register values during power-down, then circuit behavior reliability is improved, but chip area increases
Solution Approach 1:
The patent extracts and identifies the minimal subset of registers that actually require retention by analyzing data flow and dependency relationships. Instead of retaining all register values, the system selectively retains only those registers whose values are needed after power-up, thereby reducing chip area while maintaining circuit reliability for critical data preservation.
Solution Approach 2:
The patent applies different retention strategies to different registers based on their specific data flow characteristics and dependency relationships. Each register is individually analyzed to determine whether it requires retention, partial retention, or no retention, allowing optimized chip area utilization for each local region of the circuit rather than uniform full retention across all registers.
3Manufacturing precision
If manual inspection is used to select non-retention registers, then design precision is improved, but development time increases
Solution Approach 1:
The patent implements an automated analysis system that independently performs the complex task of identifying retention and non-retention registers without requiring manual designer intervention. The system automatically analyzes data flow, tracks register values through simulation, and generates retention recommendations, making the design process self-service oriented and eliminating time-consuming manual inspection while maintaining high design precision.
Solution Approach 2:
The patent replaces the mechanical manual inspection process with an automated computer-based analysis system. Instead of requiring designers to manually review and select non-retention registers, the system uses computational methods to automatically identify retention requirements through data flow analysis and simulation, substituting human expertise with automated intelligence that is both faster and consistent.
Data Source
AI summary
A retention synthesis application provides a means of analyzing a circuit design, functional test sequences, and the associated power specification to identify registers that do not need retention when a block is powered down. Reducing the number of retention registers reduces power consumption and chip area. The retention synthesis application is based, at least in part, upon symbolic simulation. In symbolic simulation, a symbol is used to represent a value that can be either 0 or 1 and the propagation of symbols is traced through the simulation.