Partial Routing Reconfiguration for IC Design Bottlenecks
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Solution Overview
Problem
Conventional routers for semiconductor integrated circuits face inefficiencies due to a rigid separation between global and detail routers and limited routing granularity, which hinders effective interaction and flexibility in routing processes.
Innovation Solution
The implementation of a routing architecture with multiple granular levels of abstraction, allowing for partial topological reconfiguration and non-uniform resource allocation, enabling routing at various levels of detail and abstraction to efficiently manage routing tasks and prioritize critical areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a rigid two-stage global route/detail route approach is used, then routing structure is simplified and easier to implement, but routing flexibility and interaction between router types is reduced
Solution Approach 1:
The patent segments the routing process into multiple independent router types (global router, detail router, switchbox router, etc.) that can operate at different granularities. Each router handles specific routing tasks independently, allowing flexible combination and interaction between different router types without requiring a rigid two-stage structure.
Solution Approach 2:
The patent implements a dynamic router selection mechanism where the appropriate router type and granularity level are chosen based on the specific routing task requirements. This allows the routing system to adaptively switch between different router configurations, enabling both simplified processing for straightforward cases and flexible interaction for complex routing scenarios.
2Device complexity
If only two levels of granularity (global routes and detail routes) are available, then routing process is simpler to manage, but routing precision and detail control is insufficient for certain types of desired routing activities
Solution Approach 1:
The patent divides the routing granularity into multiple levels beyond just global and detail routes, introducing intermediate levels such as switchbox routing and module-level routing. This segmentation allows selective application of different routing detail levels to different portions of the design, providing both simplified management for overall structure and enhanced precision for specific routing requirements.
Solution Approach 2:
The patent applies different routing granularity levels to different regions or portions of the circuit design based on local requirements. Critical areas receive more detailed routing control while less critical areas use coarser granularity, optimizing both the overall manageability and local precision of the routing process.
3Reliability
If routing is performed for entire routes or nets, then completeness of routing is ensured, but computational resources and processing time increase for complex designs
Solution Approach 1:
The patent implements partial routing where only specific portions, segments, or critical portions of routes are routed with full detail rather than entire routes. This allows the system to achieve sufficient routing completeness for functional operation while reducing computational resources by applying detailed routing only where necessary.
Solution Approach 2:
The patent applies different levels of routing effort to different portions of the design based on local importance and requirements. Critical signal paths receive complete and detailed routing while less critical paths use simplified or partial routing approaches, optimizing the balance between routing completeness and computational efficiency.
Data Source
AI summary
Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, routing can be performed for specific routes or portions of routes. Different types of representation or levels of abstraction for the routing can be used for the same net or route. Partial topological reconfiguration, refinement, or rip-up can be performed for a portion of the integrated circuit design, where the portion is smaller than an entire route or net. Non-uniform levels of routing activities or resources may be applied to route the design. Prioritization may be used to route certain portions of the design with greater levels of detail, abstraction, or resources than other portions of the design.