Partial Scan Testing Flip-Flop Segmentation ATPG
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of integrated circuits has led to the abandonment of partial scan due to compromised controllability and observability, which are costly and performance-degrading, prompting the industry to adopt full scan despite its drawbacks, including area, performance, and test costs, as well as excessive power dissipation during testing.
Innovation Solution
A test cube analysis driven partial scan scheme that identifies flip-flops to be converted to non-scan, using combinational ATPG tools to maintain the quality of full scan while reducing area, performance, and test costs by removing scan multiplexers and shortening the scan path, thus reducing power dissipation and test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full scan is adopted to ensure complete controllability and observability, then test quality is improved, but area cost increases due to insertion of multiplexers for all flip-flops
Solution Approach 1:
The patent divides the scan path into two segments: scan flip-flops that remain on the scan path and non-scan flip-flops that are removed from the scan path. This segmentation allows selective application of scan architecture, reducing the number of multiplexers needed while maintaining test quality through targeted scan coverage of critical flip-flops.
Solution Approach 2:
The patent applies partial scan action by selectively scanning only a subset of flip-flops rather than all flip-flops. This partial action reduces area cost by removing unnecessary multiplexers while the selected scan flip-flops provide sufficient controllability and observability for effective testing.
2Reliability
If full scan is implemented to achieve complete test coverage, then test quality is improved, but performance degrades due to critical path prolongation by multiplexer delay
Solution Approach 1:
The patent extracts multiplexers from the critical functional paths by removing non-scan flip-flops from the scan path. This extraction eliminates the multiplexer delay from critical paths, improving performance while scan multiplexers remain only where necessary for test quality.
Solution Approach 2:
The patent applies partial scan by selectively placing scan multiplexers only where needed for test coverage rather than throughout the entire design. This reduces the overall impact on critical paths and minimizes performance degradation.
3Reliability
If full scan is used to ensure comprehensive testing, then test quality is improved, but test time increases due to longer scan path length
Solution Approach 1:
The patent extracts unnecessary flip-flops from the scan path, creating a shorter scan chain. This reduction in scan path length directly decreases the time required for scan-in and scan-out operations, reducing overall test time while maintaining adequate test coverage through selective scan flip-flop placement.
4Reliability
If full scan is implemented to achieve complete flip-flop testing, then test quality is improved, but power dissipation increases due to excessive switching activity during test
Solution Approach 1:
The patent extracts non-essential flip-flops from the scan path, reducing the total number of flip-flops that toggle during scan operations. This reduction in switching activity directly lowers dynamic power dissipation during testing while the remaining scan flip-flops maintain adequate test coverage.
5Area of stationary object
If partial scan is applied to reduce area and improve performance, then area cost and performance are improved, but controllability and observability are compromised
Solution Approach 1:
The patent applies local quality by providing scan architecture (high controllability and observability) only to specific critical flip-flops that benefit most from scanning, while non-critical flip-flops are removed from the scan path. This localized application of scan maintains adequate overall controllability and observability while reducing area cost.
6Reliability
If sequential ATPG is used to maintain test quality with partial scan, then test quality is preserved, but computational cost becomes unaffordable given circuit complexity
Solution Approach 1:
The patent applies partial scan with a focus on scanning only the most critical flip-flops, rather than attempting to scan all flip-flops or using computationally intensive sequential ATPG. This partial approach achieves adequate test quality through targeted scan coverage of flip-flops that have the greatest impact on test effectiveness.
Data Source
AI summary
Exemplary method, computer-accessible medium, test architecture, and system can be provided for a partial-scan test of at least one integrated circuit. For example, it is possible to obtain a plurality of test cubes using a first combinational automatic test pattern generation (ATPG) and identify at least one flip-flop of the integrated circuit using the test cubes to convert to a non-scan flip-flop and facilitate the partial-scan test to utilize the cubes without a utilization of a sequential ATPG or a second combinational ATPG.