Partial Select Gate Drain Program Disturb Reduction
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Solution Overview
Problem
In non-volatile memory systems, program disturb occurs due to the proximity of memory strings with partial select gate drains, especially at higher program states, which can lead to increased memory cell interference and reduced scalability.
Innovation Solution
A memory controller is used to apply varying voltage levels to full select gate drains and bitlines, reducing the bias voltage on selected memory cells during higher program states to minimize program disturb on adjacent unselected partial select gate drains, while maintaining efficient programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory strings with partial select gate drains are used to increase density, then storage capacity is improved, but program disturb on adjacent memory cells increases
Solution Approach 1:
The patent applies different voltage levels to different regions of the select gate drain. Specifically, the control gate voltage is dynamically adjusted based on the programming state: higher voltages (e.g., 5V) are applied to selected memory cells requiring programming, while lower voltages (e.g., 3.3V) are applied to unselected adjacent cells. This localized voltage differentiation reduces program disturb on neighboring partial select gate drains while maintaining effective programming on target cells, thus resolving the contradiction between increased storage capacity and reduced program disturb.
2Quantity of substance
If higher program states are implemented to increase data density, then storage efficiency is improved, but interference between adjacent memory cells increases
Solution Approach 1:
The patent changes the voltage parameter dynamically based on the programming state. For higher program states that require more aggressive programming voltages, the system adjusts the select gate drain voltage to prevent excessive interference. Specifically, when programming to higher states, the control gate voltage is modulated to maintain the necessary programming strength while limiting the electric field spread to adjacent cells. This parameter adjustment allows high-density storage implementation while controlling inter-cell interference.
3Speed
If full voltage is applied to select gate drain for all program states, then programming speed is improved, but program disturb on unselected cells increases
Solution Approach 1:
The patent implements dynamic voltage adjustment on the select gate drain based on the specific programming operation being performed. Instead of applying a static full voltage to all cells, the system dynamically switches between different voltage levels (e.g., 5V for selected cells, 3.3V for unselected cells) during the programming process. This dynamic control maintains fast programming speeds for selected cells while reducing program disturb on unselected adjacent cells, thus resolving the speed versus program disturb contradiction.
Data Source
AI summary
Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.