Partial Self-Refresh DRAM for SSD Power Reduction
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Solution Overview
Problem
Conventional SSDs face challenges in reducing power consumption while maintaining quick response times, as they either need to continuously supply power to DRAM to prevent data loss or shut off power to DRAM, which slows down data access when requests from the host occur after a period of inactivity, and must manage defective memory portions and metadata integrity during power loss.
Innovation Solution
The SSD employs a partial self-refresh DRAM that shuts off power to non-essential areas during inactivity, holding critical data in a continuously powered area for quick access, and uses a layered address translation table to optimize data storage and retrieval, allowing for efficient power management and rapid response to host requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is continuously supplied to DRAM to prevent data loss, then data integrity is maintained, but power consumption increases
Solution Approach 1:
The DRAM is divided into two distinct areas: a first area continuously supplied with power to maintain critical data, and a second area where power supply can be shut off to reduce consumption. This segmentation allows the system to maintain data integrity for essential operations while significantly reducing power usage during idle periods.
Solution Approach 2:
Different parts of the DRAM receive different power supply treatments based on their importance. The first area (critical data) receives continuous power to ensure reliability, while the second area (non-essential data) receives intermittent power to reduce consumption. This local differentiation resolves the contradiction between maintaining data integrity and reducing power usage.
2Use of energy by moving object
If power is shut off to DRAM to reduce power consumption, then power usage decreases, but data access speed slows down when host requests occur after inactivity
Solution Approach 1:
By segmenting DRAM into continuously powered and intermittently powered areas, the system ensures that critical data remains accessible at full speed while non-critical data can be powered down. This resolves the contradiction by maintaining fast access for essential operations while reducing overall power consumption.
Solution Approach 2:
The system performs preliminary actions by keeping critical data in the continuously powered first area of DRAM before any host request occurs. This ensures that when a host request arrives after inactivity, the essential data is already ready for immediate access, maintaining speed while allowing power reduction in non-critical areas.
3Reliability
If all DRAM data is saved to nonvolatile memory before power shutdown, then data loss is prevented, but the complexity of data management increases
Solution Approach 1:
The patent segments data into critical and non-essential categories, storing critical data in the continuously powered first area of DRAM that doesn't require saving to nonvolatile memory during power shutdown. This segmentation simplifies data management by eliminating the need to save and restore all DRAM data, reducing complexity while still preventing data loss for essential information.
Solution Approach 2:
The patent extracts critical data from the general DRAM pool and places it in the continuously powered first area, separating it from non-essential data in the second area. This extraction eliminates the need to manage saving/restoring operations for critical data, reducing overall data management complexity while maintaining reliability.
Data Source
AI summary
According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.