Partial Sidewall Liner for Void-Free Copper Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming void-free copper interconnects with a ruthenium seed enhancement liner is the difficulty in chemical-mechanical polishing, which leads to copper loss at the top interface, resulting in high line resistance due to galvanic corrosion.
Innovation Solution
A partial sidewall seed enhancement liner is used, where the liner is present only along the middle portion of the sidewalls, avoiding the top and bottom, to prevent galvanic corrosion during chemical-mechanical polishing, allowing for void-free copper fill and maintaining high copper volume without Cu loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a Ru liner is deposited to prevent barrier exposure during Cu plating, then void-free Cu fill is achieved, but Cu loss occurs during CMP due to galvanic corrosion
Solution Approach 1:
The patent applies local quality by selectively positioning the Ru liner only in the middle portion of the sidewalls rather than providing continuous coverage. This localized placement maintains the critical function of preventing void formation during Cu plating in the middle section while eliminating the harmful galvanic corrosion effect at the top and bottom portions where the liner is absent.
Solution Approach 2:
The patent segments the Ru liner coverage into distinct regions - present in the middle portion of sidewalls and absent from the top and bottom portions. This segmentation allows the liner to perform its void-prevention function where needed while avoiding the galvanic corrosion problem at interfaces with the dielectric and Cu fill.
2Quantity of substance
If a Ru liner is deposited along the sidewalls to prevent barrier exposure, then Cu volume is maximized, but line resistance increases due to Cu loss at top interface
Solution Approach 1:
The patent uses local quality to place the Ru liner only in the middle portion of sidewalls, preserving Cu volume where the liner provides void prevention while eliminating Cu loss at the top interface. This selective placement maintains high Cu volume for low resistance while avoiding the galvanic corrosion that would increase line resistance.
3Manufacturing precision
If a Ru liner is deposited to prevent barrier exposure during plating, then sidewall voids are prevented, but CMP difficulty increases due to galvanic corrosion
Solution Approach 1:
The patent applies local quality by restricting the Ru liner to the middle portion of sidewalls, maintaining void prevention capability where the liner is present while eliminating galvanic corrosion at the top and bottom portions. This resolves the CMP difficulty caused by galvanic corrosion while preserving sidewall void prevention.
Solution Approach 2:
The patent extracts the Ru liner from problematic locations (top and bottom portions of sidewalls) while retaining it in beneficial locations (middle portion). This extraction eliminates the galvanic corrosion issue that complicates CMP while preserving the void prevention function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reliable, low-line resistance copper interconnects with lower via resistance and eliminates copper loss during CMP, ensuring a coplanar top surface with the dielectric and a unique flanged configuration of the interconnects.
Implementation Method 1
the galvanic corrosion of Cu during Ru CMP can result in Cu loss at a top interface of the interconnect
Implementation Method 2
chemical-mechanical polishing (CMP) of Cu interconnects containing a Ru liner is difficult
Data Source
AI summary
An interconnect structure and techniques for fabrication thereof having a partial sidewall liner are provided. In one aspect, the interconnect structure includes: a substrate; a dielectric disposed on the substrate having at least one feature present therein; a barrier layer lining the at least one feature; a seed enhancement liner disposed over the barrier layer along sidewalls of the at least one feature, wherein the seed enhancement liner is present along only a middle portion of the sidewalls of the at least one feature; and at least one interconnect disposed within the at least one feature over the barrier layer and the seed enhancement liner.