Partial Super Block Allocation for Storage Device Current Optimization

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Solution Overview

Problem

Current storage devices face challenges in reducing current consumption during program and read operations, leading to inefficiencies in data storage and retrieval processes.

Innovation Solution

The implementation of a memory controller that allocates partial super blocks with different numbers of partial blocks across memory devices, allowing for parallel operations across memory blocks with varying numbers of physical pages in an erase state, thereby optimizing the program and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If memory devices perform program operations on memory blocks with the same number of physical pages, then operation simplicity is maintained, but current consumption cannot be optimized

Engineering Contradiction:
Improvecurrent consumptionVSAvoidoperation management complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent divides memory blocks into multiple partial blocks, where each partial block contains a subset of physical pages. This segmentation allows the memory controller to selectively activate only the partial blocks needed for current operations, reducing overall current consumption while maintaining manageable complexity through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different operational characteristics to different partial blocks within memory devices. By assigning partial blocks with different numbers of physical pages to different operational modes or activation states, the system optimizes current consumption locally without requiring complete reconfiguration of the entire memory system.

Inventive Principle:
Principle #3Local quality

2Productivity

If memory devices operate in parallel with uniform block structures, then operational efficiency is maintained, but flexibility in power management is reduced

Engineering Contradiction:
Improveoperational efficiencyVSAvoidpower management flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent enables dynamic configuration of partial super blocks by allowing the memory controller to selectively activate or deactivate specific partial blocks based on operational requirements. This dynamic approach maintains parallel operational efficiency while providing flexibility in power management through adaptive resource allocation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The partial block structure serves multiple functions: it enables parallel operations for high productivity, allows selective activation for power optimization, and provides flexible configuration for different operational modes. This multi-functionality resolves the contradiction between operational efficiency and power management flexibility.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If all memory blocks are activated for parallel operations, then data storage throughput is maximized, but power consumption increases

Engineering Contradiction:
Improvedata storage throughputVSAvoidtotal current consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements partial action by activating only the necessary partial blocks required for current data storage operations rather than all memory blocks. This approach maintains adequate data storage throughput by processing data in parallel across active partial blocks while reducing total current consumption by leaving inactive partial blocks in a low-power state.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11593009B2Storage device and operating method thereof
Publication Date: 2023.02.28 SK HYNIX INC
  • US11593009B2 patent drawing
  • US11593009B2 patent drawing
  • US11593009B2 patent drawing

AI summary

A memory controller includes: a block manager for allocating a plurality of partial super blocks each including partial blocks in different memory blocks; and an operation controller for controlling a plurality of memory devices to perform, in parallel, a program operation of sequentially storing data in physical pages in each of the partial blocks in a partial super block selected from the plurality of partial super blocks. Each of the plurality of partial super blocks includes partial blocks in memory blocks having different numbers of physical pages having an erase state.