Partial Testing of 3D ICs to Reduce Scrap
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Solution Overview
Problem
Current methodologies for testing three-dimensional semiconductor ICs result in high scrap rates and low yields due to the practice of testing only completed assemblies, which leads to wasted time and materials when defects or errors are introduced during assembly.
Innovation Solution
Implementing systems and methods for testing partially completed three-dimensional ICs at various assembly stages using Design for Testing (DFT), Design for Partial Wafer Test, partial probing, partial IC probe cards, and partial IC test equipment to identify defects early in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If testing is performed only on completed three-dimensional IC assemblies, then the testing process is simple and straightforward, but the scrap rate increases and yield decreases due to undetected defects from individual dice or assembly errors
Solution Approach 1:
The patent divides the testing process into multiple segments: individual dice testing before assembly, and partial stack testing during assembly. This segmentation allows defects to be detected at different stages, preventing defective dice from being assembled and enabling early detection of assembly errors, thereby improving yield without requiring complete assembly testing
Solution Approach 2:
The patent implements preliminary testing of individual dice before they are assembled into three-dimensional stacks. This preliminary action identifies defective dice in advance, preventing them from being incorporated into final assemblies. The system also performs preliminary stacking of known good dice, allowing early detection of potential assembly issues before full completion
2Loss of time
If individual dice are tested in isolation before assembly, then defective dice can be identified early, but the testing must be repeated after assembly leading to increased testing time and cost
Solution Approach 1:
The patent implements a feedback mechanism where test results from individual dice are used to determine which dice are suitable for assembly. The system provides feedback on the quality of stacked assemblies, allowing for identification of assembly errors. This feedback loop enables targeted retesting only of potentially defective assemblies rather than requiring universal retesting of all completed stacks
Solution Approach 2:
The patent applies partial testing strategies where not all completed assemblies require full retesting. Instead, the system performs selective testing based on preliminary results, testing only those assemblies that show potential issues or are subject to specific quality thresholds. This partial action approach reduces overall testing time while maintaining adequate defect detection accuracy
3Productivity
If wafers are stacked before testing, then three-dimensional assembly can be completed earlier, but any assembly errors or defective dice result in complete waste of the entire stack
Solution Approach 1:
The patent performs preliminary testing and selection of individual dice before stacking, ensuring that only known good dice are assembled. The system also implements preliminary stacking processes where dice are temporarily assembled in controlled sequences, allowing for verification before final commitment. This preliminary action prevents defective dice from being permanently incorporated into final stacks, reducing material waste
Solution Approach 2:
The patent segments the stacking process into multiple controllable stages, allowing for intermediate verification points. Rather than completing entire stacks before testing, the system performs partial stacking and testing at intermediate stages, enabling early detection and correction of assembly errors. This segmentation reduces the penalty of complete stack rejection by limiting the scope of potential failures to smaller sub-assemblies
Data Source
AI summary
Systems and methods are provided for testing partially completed three-dimensional ICs. Example methods may incorporate one or more of the following features: design for testing (DFT); design for partial wafer test; design for partial probing; partial IC probecards; partial IC test equipment; partial IC quality determinations; partial IC test optimization; and partial test optimization. Other aspects may also be included. Systems and methods incorporating these features to test partially completed three-dimensional ICs may result in saved time and effort, and less scraped material, as the partial device is not built any further when a bad partial device is detected. This results in lower costs and higher yield.