Partial Timing Model for Gate Level Simulation
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Solution Overview
Problem
The complexity of modern electronic circuits makes full gate level simulations time-consuming and resource-intensive, especially when using semiconductor intellectual property cores, as existing methods lack accurate timing across different abstraction levels, leading to potential design flaws being undetected.
Innovation Solution
A system that performs partial gate level simulations by generating a partial timing model, cutting a circuit at timing path boundaries, and overlaying a simplified representation over the remaining circuit, allowing for focused verification of critical timing paths while reducing overall simulation time and resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full gate level simulation is performed on complex electronic circuits, then design verification accuracy is improved, but simulation time and computational resources are excessively consumed
Solution Approach 1:
The circuit design is segmented into two portions: a first portion containing IP cores represented by behavioral models, and a second portion containing remaining circuitry represented by gate level netlists. This segmentation allows different simulation approaches to be applied to different portions, reducing overall simulation time while maintaining verification accuracy for critical paths.
Solution Approach 2:
Different levels of simulation detail are applied to different portions of the circuit. The second portion (remaining circuitry) receives full gate level simulation with detailed timing analysis, while the first portion (IP cores) uses behavioral models. This local differentiation optimizes the balance between verification thoroughness and simulation efficiency.
2Loss of time
If gate level simulation is omitted for IP core blocks, then simulation time is reduced, but design flaws at interfaces may go undetected
Solution Approach 1:
Interface circuits are introduced as intermediaries between the behavioral model portion and the gate level netlist portion. These interface circuits ensure proper signal handshaking and timing synchronization, allowing accurate verification of interface interactions without requiring full gate level simulation of the IP cores themselves.
3Productivity
If mixed levels of abstraction are used for co-simulation, then simulation efficiency is improved, but timing accuracy across abstraction boundaries is compromised
Solution Approach 1:
The interface circuits are instantiated twice: once connected to the behavioral model representation and once connected to the gate level netlist representation. This copying approach allows the interface logic to mediate between the two abstraction levels, ensuring timing accuracy is maintained across the boundary while preserving simulation efficiency benefits of mixed abstraction.
Data Source
AI summary
Various apparatuses, methods and systems for creating an integrated circuit and performing a gate level simulation of a circuit are disclosed herein. For example, some embodiments of the present invention provide a system for performing a gate level simulation of a circuit including a computer system, a design verification tool and an output device. The design verification tool, executable on the computer system, includes a simulator and a partial timing model generator. The partial timing model generator is operable to generate a representation of the circuit for simulation by cutting a first portion of a circuit out of a full gate level netlist for the circuit and leaving a second portion of the circuit represented by the full gate level netlist, and to overlay a simplified representation of the first portion of the circuit over the representation of the circuit. The first portion of the circuit is cut out at timing paths. The simulator is operable to perform a gate level simulation of the circuit based on the representation of the circuit. The output device is connected to the computer system and is operable to provide an indication of a result of the gate level simulation of the circuit.