Partial Through-Substrate Vias for 3D Semiconductor Integration
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Solution Overview
Problem
Conventional two-dimensional integrated circuit devices face limitations in miniaturization and functionality due to their lack of vertical integration, which restricts the compactness and performance of consumer electronic devices like smartphones and tablets.
Innovation Solution
The development of semiconductor devices with partially extending through-substrate vias (TSVs) that provide electrical interconnectivity between layers, allowing for three-dimensional integration by bonding a semiconductor wafer to a carrier wafer with an adhesive and forming vias that extend from the surface to an etch stop within the substrate, enabling additional routing and integration of components near the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional two-dimensional integrated circuit devices are used, then manufacturing and design are simpler, but device compactness and functionality are limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar integration to three-dimensional vertical integration by implementing through-substrate vias (TSVs) that extend vertically through the substrate. This dimensional change enables stacking multiple active layers vertically, thereby increasing device functionality and compactness while managing the associated manufacturing complexity through systematic process design
2Volume of moving object
If through-substrate vias are implemented for vertical integration, then device compactness and functionality increase, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the etch stop layer within the substrate before creating the through-substrate vias. This pre-positioned etch stop serves as a predetermined termination point that guides the via formation process, ensuring consistent via depth and preventing over-etching, thereby simplifying the overall manufacturing process despite the increased vertical integration complexity
3Reliability
If vias extend completely through the substrate, then electrical interconnectivity is achieved, but routing flexibility near the surface is reduced
Solution Approach 1:
The patent segments the via structure into two distinct parts: through-substrate vias that extend completely through the substrate for reliable electrical interconnectivity, and partial vias that extend only partially through the substrate to terminate at the etch stop layer. This segmentation allows different via types to serve different functions - TSVs for through-silicon interconnection and partial vias for surface-level routing flexibility, enabling both reliability and adaptability
Data Source
AI summary
Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.