Partial Via Plug Interconnects for Wafer Level Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Wafer level packaging techniques, such as Through Silicon Via (TSV), face challenges with long processing times, high costs, and stress-induced yield reduction due to the need for deep via etching, which hinders the production of dense, reliable, and cost-effective electronic packages.
Innovation Solution
The method involves forming an interconnect through a support substrate with partial via plugs and heavily doped regions, allowing for electrical connections between substrate surfaces without extending through contacts, thereby reducing processing time and cost while maintaining reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Through Silicon Via (TSV) process is used to etch deep vias for wafer level packaging, then integration and stacking of wafers is enabled, but processing time increases significantly
Solution Approach 1:
The via structure is segmented into two parts: a shallow etched portion and a heavily doped region that extends deeper into the substrate. This segmentation allows the conductive path to be achieved without requiring a single deep etched via, thereby reducing processing time while maintaining integration capability
Solution Approach 2:
The invention changes the electrical parameters of the substrate by heavily doping a region to create a conductive path. Instead of relying solely on physical through-via etching, the electrical conductivity is enhanced through doping, allowing current to pass through the substrate without requiring complete physical penetration
2Adaptability or versatility
If Through Silicon Via (TSV) process is used for deep via etching, then wafer stacking is achieved, but manufacturing cost increases
Solution Approach 1:
The via formation process is segmented into shallow etching followed by heavy doping. This avoids the need for expensive deep etching equipment and processes while still achieving the necessary conductive path for wafer stacking applications
Solution Approach 2:
The mechanical etching process is replaced partially with a doping process. Instead of mechanically removing material to create a deep conductive path, the invention uses chemical doping to create electrical conductivity, which is generally less costly and simpler to implement
3Reliability
If Through Silicon Via (TSV) process is used for deep via etching, then electrical connection is established, but stress increases which impacts yield
Solution Approach 1:
The conductive path is segmented into a shallow etched via portion and a heavily doped region. This segmentation reduces the mechanical stress associated with deep etching while maintaining electrical connectivity through the combination of the via and the doped conductive region
Solution Approach 2:
The invention changes the electrical parameters through doping rather than relying solely on mechanical via formation. This parameter change approach reduces the mechanical stress on the substrate while achieving the desired electrical connection for reliable device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances manufacturing efficiency and reduces costs by eliminating the need for deep via etching, achieving desired resistance values, and improving package density and reliability.
Implementation Method 1
The second portion of the interconnect is heavily doped with dopants of a first polarity type
Data Source
AI summary
A method for forming a device is disclosed. A support substrate having first and second major surfaces is provided. An interconnect is formed through the first and second major surfaces in the support substrate. The interconnect has first and second portions. The first portion extends from one of the first or second major surfaces and the second portion extends from the other of the first and second major surfaces. The interconnect includes a partial via plug having a conductive material in a first portion of the interconnect. The via plug has a bottom at about an interface of the first and second portions. The second portion of the interconnect is heavily doped with dopants of a first polarity type.