Partial Wafer Singulation for Embedded System in Package
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Solution Overview
Problem
Semiconductor devices face delamination and cracking issues due to high thermal stress, particularly at the interface between insulating materials and semiconductor dies, leading to reduced lifespan and performance.
Innovation Solution
The implementation of partial singulation in wafer level embedded systems, where the wafer is partially singulated and encapsulant is deposited around the semiconductor die to reduce stress, combined with thermal interface materials and improved interconnect structures to enhance heat dissipation and mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the wafer is fully singulated into individual die, then manufacturing efficiency is improved, but thermal stress concentration increases leading to delamination and cracking
Solution Approach 1:
The wafer is partially singulated into individual die only in specific regions where needed, rather than completely separating all die. This selective segmentation maintains the structural integrity of the wafer while still enabling efficient manufacturing processes, thereby reducing thermal stress concentration that would otherwise lead to delamination and cracking.
Solution Approach 2:
The patent employs a composite structure where the wafer maintains its original material properties in unsingulated regions while incorporating singulated die in specific areas. This composite approach allows the wafer to benefit from both the structural stability of the intact wafer and the manufacturing efficiency of singulated die, resolving the contradiction between productivity and reliability.
2Temperature
If thermal interface materials and improved interconnect structures are added, then thermal performance is enhanced, but device complexity increases
Solution Approach 1:
Thermal interface materials are introduced as intermediary substances between heat-generating components and heat dissipation structures. These materials facilitate efficient heat transfer without requiring fundamental changes to the existing device architecture, thereby enhancing thermal performance while minimizing increases in device complexity.
Solution Approach 2:
The patent modifies thermal parameters by introducing materials with optimized thermal conductivity properties and designing interconnect structures with improved thermal pathways. These parameter changes enhance heat dissipation capability through material selection and structural optimization rather than through complex system redesign.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces delamination and cracking, enhances thermal performance, and extends the lifespan of semiconductor devices by mitigating thermal stress and improving mechanical integrity.
Implementation Method 1
delamination and cracking in wafer level embedded system in packages
Implementation Method 2
thermal interface materials and improved interconnect structures to enhance heat dissipation
Data Source
AI summary
A semiconductor device includes a semiconductor wafer including a plurality of first semiconductor die. An opening is formed partially through the semiconductor wafer. A plurality of second semiconductor die is disposed over a first surface of the semiconductor wafer. An encapsulant is disposed over the semiconductor wafer and into the opening leaving a second surface of the semiconductor wafer exposed. A portion of the second surface of the semiconductor wafer is removed to separate the first semiconductor die. An interconnect structure is formed over the second semiconductor die and encapsulant. A thermal interface material is deposited over the second surface of the first semiconductor die. A heat spreader is disposed over the thermal interface material. An insulating layer is formed over the first surface of the semiconductor wafer. A vertical interconnect structure is formed around the first semiconductor die. Conductive vias are formed through the first semiconductor die.