Partial Width Link State Transitions in High Performance Interconnects
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly as the number of processing devices grows, leading to complexity and inefficiencies in communication between components.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and power management, to enable efficient data transfer and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then electrical communication is simplified, but bandwidth and communication speed are insufficient for high-performance computing
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links instead of a shared multi-drop bus. Each link operates independently with dedicated bandwidth, enabling simultaneous communications between multiple device pairs. This segmentation resolves the bandwidth limitation of traditional buses while maintaining electrical communication simplicity through standardized link interfaces.
Solution Approach 2:
The architecture transitions from a single-dimensional shared bus to a multi-dimensional mesh-like topology where devices can communicate through multiple paths. This dimensional change provides alternative communication routes, increasing effective bandwidth and communication speed without requiring a single complex high-speed bus.
2Productivity
If the number of processing devices increases, then computing power grows, but communication complexity and power consumption increase
Solution Approach 1:
The interconnect architecture implements dynamic power management where link power states are adjusted based on actual communication needs. Links can transition between active, idle, and power-down states, allowing the system to scale computing power while dynamically optimizing power consumption to match the actual workload and communication requirements.
Solution Approach 2:
The system changes operational parameters such as link width, data rate, and power state based on communication demand. When fewer devices are actively communicating, parameters are adjusted to reduce power consumption while maintaining the capability to scale to higher computing power when full communication capacity is needed.
3Speed
If full-width link transitions are used, then data transfer speed is maximized, but power consumption increases during state changes
Solution Approach 1:
Instead of always transitioning links through full-width state changes, the architecture uses partial-width transitions when possible. Links can change width incrementally (e.g., from 256-bit to 128-bit to 64-bit) during state transitions, reducing the energy required for transitions while still achieving full bandwidth when needed for actual data transfer.
Solution Approach 2:
The system employs periodic width changes and idle states rather than continuous full-width operation. Links can periodically adjust their width based on traffic patterns, entering lower-power partial-width or idle states during periods of low utilization, then transitioning back to full width when high-speed transfer is needed, thereby reducing overall energy loss during transitions.
Data Source
AI summary
An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.