Partial Width Memory Modules for Signal Integrity
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Solution Overview
Problem
In computer systems, the impedance discontinuity and bus loading caused by dual inline memory modules (DIMMs) in parallel memory bus topologies lead to signal integrity issues, limiting the maximum number of DIMMs that can be supported as the memory bus frequency increases, forcing designers to choose between memory bandwidth and capacity.
Innovation Solution
The implementation of multi-rank, partial width memory modules with a memory controller and memory bus, where the memory module has fewer data pins than the memory bus, allowing for multiple ranks of memory circuits to operate with reduced data pin connections, and optionally using buffer chips to transform data signals, enabling efficient data transmission across a subset of the memory bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple DIMMs are connected in parallel memory bus topology, then memory capacity is increased, but signal integrity deteriorates due to impedance discontinuity and bus loading
Solution Approach 1:
The patent divides the memory module into multiple ranks, where each rank connects to a subset of data bus lines rather than all lines. This segmentation reduces the number of simultaneous connections each DIMM makes to the memory controller, thereby reducing bus loading and impedance discontinuity effects while maintaining total memory capacity through multiple ranks.
2Productivity
If memory bus frequency is increased, then memory bandwidth is improved, but the maximum number of supported DIMMs decreases
Solution Approach 1:
By segmenting the memory module into multiple ranks with partial data bus connections, the patent enables more DIMMs to be supported at higher frequencies. Each rank uses a subset of data lines, reducing the overall bus loading at high frequencies and allowing the system to maintain both high bandwidth and support for multiple DIMMs.
3Productivity
If data bus width of DIMM matches memory bus, then data transmission efficiency is improved, but device complexity increases due to requiring multiple DRAM circuits in parallel
Solution Approach 1:
The patent implements partial width DIMMs where the data bus width of individual DIMMs is less than the full memory bus width. Instead of requiring multiple DRAM circuits per DIMM to match the full bus width, each DIMM uses a partial subset of data lines, reducing device complexity while maintaining efficient data transmission through the allocated subset.
Data Source
AI summary
A system is provided for multi-rank, partial-width memory modules. A memory controller is provided. Additionally, a memory bus is provided. Further, a memory module with a plurality of ranks of memory circuits is provided, the memory module including a first number of data pins that is less than a second number of data pins of the memory bus.