Partial Wrap Around Top Contact for Semiconductor FET Devices
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Solution Overview
Problem
Conventional contact structures in semiconductor FET devices face challenges in achieving perfect alignment, leading to high contact resistance due to zero or negative enclosure scenarios, especially as device dimensions scale.
Innovation Solution
The design incorporates a lower portion of the top contact that partially wraps around the bottom contact, allowing for zero or negative enclosure, which increases contact area and reduces resistance, and involves a method of forming this structure with specific interlayer dielectrics and liners to facilitate this configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact structures are used with perfect alignment, then contact resistance is minimized, but manufacturing precision becomes increasingly difficult as device dimensions scale
Solution Approach 1:
The contact structure transitions from a conventional planar contact to a three-dimensional wrap-around configuration. The top contact wraps around the bottom contact from the horizontal plane into the vertical dimension, creating multiple contact surfaces (top surface and sidewalls) that collectively reduce contact resistance while compensating for alignment variations in the horizontal plane.
Solution Approach 2:
The top contact is configured to wrap around and partially enclose the bottom contact, creating a nested structure where the top contact surrounds a portion of the bottom contact. This nesting increases the effective contact area and provides multiple parallel conduction paths, reducing contact resistance while being tolerant to alignment variations.
2Productivity
If device dimensions are scaled down, then device density and integration are improved, but alignment issues between contact and metal line worsen
Solution Approach 1:
By extending the contact structure into the vertical dimension with wrap-around geometry, the invention creates additional contact area that compensates for reduced horizontal alignment precision in scaled devices. The sidewall contact surfaces provide alternative conduction paths that are less sensitive to horizontal misalignment.
Solution Approach 2:
The contact structure is segmented into distinct top and bottom contact portions with the top contact wrapping around the bottom contact. This segmentation allows each portion to be optimized independently and creates multiple discrete contact interfaces that collectively maintain low resistance even when individual interfaces have alignment variations.
3Ease of manufacture
If zero or negative enclosure is accepted, then manufacturing complexity is reduced, but contact resistance increases due to poor alignment
Solution Approach 1:
The wrap-around contact structure utilizes the vertical dimension to create sidewall contact surfaces that are insensitive to horizontal alignment variations. This allows zero or negative enclosure configurations to maintain low contact resistance by providing alternative conduction paths through the vertical sidewalls rather than relying solely on horizontal overlap.
Data Source
AI summary
Contact designs for semiconductor FET devices are provided. In one aspect, a contact structure includes: a metal line(s); a first ILD surrounding the metal line(s), wherein a top surface of the first ILD is recessed below a top surface of the metal line(s); a liner disposed on the first ILD and on portions of the metal line(s); a top contact(s) disposed over, and in direct contact with, the metal line(s), wherein an upper portion of the top contact(s) has a width W1 and a height H1, wherein a lower portion of the top contact(s) has a width W2 and a height H2, and wherein W1<W2 and H1>H2; and a second ILD disposed over the liner and surrounding the top contact(s). A semiconductor FET device and methods for fabrication thereof are also provided.