Partial Write Cache Line Eviction for STT-RAM Energy Reduction
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Solution Overview
Problem
Non-volatile memory devices like STT-RAM consume significant energy for writes and experience write latency, making them inefficient in hierarchical cache management systems where cache line replacements are frequent.
Innovation Solution
Implement a technique that selects the cache line with the least number of differing bits from an incoming cache line for eviction, using a partial write operation to minimize write operations and leverage the Least Recently Used (LRU) list to identify candidate cache lines for replacement, thereby reducing the number of writes needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a cache line is replaced in a hierarchical cache management system, then the new cache line becomes available in the lower level cache, but significant energy is consumed and write latency occurs
Solution Approach 1:
The patent changes the parameter of write operation from full write to partial write. By comparing the incoming cache line with candidate eviction cache lines and identifying only the differing bits, the system performs write operations only on those specific bits. This parameter change from complete to selective writing significantly reduces energy consumption while maintaining the cache replacement functionality.
2Reliability
If a full write operation is performed during cache line replacement, then the incoming cache line is fully written to the first memory device, but write latency increases
Solution Approach 1:
The patent segments the write operation into identifying only the differing bits between the incoming cache line and the eviction cache line. Instead of writing all bits, the system divides the write operation into selective bit-level writes. This segmentation maintains data integrity by ensuring all necessary changes are made while reducing the total number of write operations and associated latency.
3Reliability
If cache lines are frequently replaced in STT-RAM, then the cache remains updated with current data, but the endurance of the memory device deteriorates
Solution Approach 1:
The patent changes the write operation parameter from full-write to partial-write based on bit comparison. By performing write operations only on differing bits rather than complete cache lines, the frequency and volume of write operations to the STT-RAM device are significantly reduced. This parameter change preserves cache data currency while extending memory device endurance by minimizing wear from frequent writes.
Data Source
AI summary
Provided are an apparatus, system, and method to determine a cache line in a first memory device to be evicted for an incoming cache line in a second memory device. An incoming cache line is read from the second memory device. A plurality of cache lines in the first memory device are processed to determine an eviction cache line of the plurality of cache lines in the first memory device having a least number of bits that differ from corresponding bits in the incoming cache line. Bits from the incoming cache line that are different from the bits in the eviction cache line are written to the eviction cache line in the first memory device.