Partial Write Management in Multi-Tiled Compute Engines
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Solution Overview
Problem
In multi-tiled compute engines, partial writes to cache lines across different tiles can lead to race conditions and memory inconsistencies, particularly when threads write to the same or adjacent bytes without synchronization, and existing techniques struggle to maintain memory coherence and manage partial writes effectively.
Innovation Solution
Implementing a method that ensures memory coherence by flushing L3 caches at synchronization points, such as using fence messages or pipe-control commands, and employing Open CL memory model requirements to maintain per-thread read-write ordering, even across different tiles, while also addressing memory compression issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If threads write to the same address byte in cache without synchronizing across different tiles, then parallel execution speed is improved, but memory consistency and ordering are compromised due to race conditions
Solution Approach 1:
The system performs preliminary actions by establishing per-thread read-write ordering rules before parallel execution begins. The memory management unit is configured to track and enforce ordering of memory operations for each thread independently, ensuring that read-after-write dependencies are maintained without requiring synchronization barriers between tiles.
Solution Approach 2:
The memory system is segmented into per-thread ordering tracks, where each thread maintains its own read-write ordering sequence. This segmentation allows different threads to execute in parallel while preserving individual thread memory ordering requirements, resolving the contradiction between parallel speed and memory consistency.
2Reliability
If L3 cache flushing is performed at every synchronization point to maintain memory coherence, then memory consistency across tiles is improved, but execution performance deteriorates due to frequent cache flushes
Solution Approach 1:
Instead of flushing the entire L3 cache at every synchronization point, the system performs partial actions by only flushing specific cache lines or regions that are actually modified. The memory management unit tracks which cache lines require coherence maintenance and selectively flushes only those, reducing the performance overhead while maintaining memory coherence.
Solution Approach 2:
The cache coherence mechanism applies local quality by treating different cache lines with different flush policies based on their access patterns and modification status. Only the specific local regions that require coherence are flushed, rather than performing global cache flushes, thereby improving execution performance while maintaining necessary memory coherence.
3Reliability
If per-thread read-write ordering is enforced across all memory operations, then memory model compliance is improved, but parallel processing efficiency deteriorates due to increased synchronization overhead
Solution Approach 1:
Each thread independently manages its own read-write ordering through hardware-supported per-thread tracking mechanisms. The memory management unit automatically enforces ordering for each thread without requiring inter-thread synchronization or software intervention, allowing threads to self-service their memory ordering requirements while maintaining OpenCL compliance.
Data Source
AI summary
Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.