Partially Coherent Memory Transfer via Message Queues
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Solution Overview
Problem
Large-scale shared memory architectures face performance limitations due to lack of coherence across a memory fabric, leading to inefficient inter-processor communication and increased traffic, especially when using non-coherent memory systems where data consistency is not implicitly synchronized across nodes.
Innovation Solution
Implementing a partially coherent messaging system where target location addresses within the local memory of a receiving SMP node are used, allowing direct data transfer across a non-coherent memory fabric, reducing unnecessary traffic and ensuring data consistency by using push and pull operations to update and invalidate cache entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a non-coherent memory fabric is used to scale shared memory to support a very large number of processors, then the system can achieve large-scale data sharing and avoid the performance limitations of coherent cache protocols, but data consistency is not implicitly synchronized across nodes leading to inefficient inter-processor communication
Solution Approach 1:
The patent introduces message queues as intermediary structures that mediate data transfer between SMP nodes. Send queues in the originating node and receive queues in the destination node act as buffers and coordination points, enabling reliable data transfer across the non-coherent fabric without requiring full coherence protocols. The queue management software serves as a mediator that handles the complexity of data consistency.
Solution Approach 2:
The patent changes the coherence model parameter from full coherence to partial coherence. Instead of maintaining coherence across all memory accesses across nodes, the system only maintains coherence for data that has been explicitly transferred through the message queue mechanism. This parameter change allows scaling to many more processors while maintaining consistency for transferred data.
2Reliability
If full cache coherence protocols are implemented across SMP nodes, then data consistency is maintained, but the system complexity and performance overhead increase significantly
Solution Approach 1:
The patent segments the coherence problem into two parts: (1) each SMP node maintains full coherence within its own coherence domain, and (2) inter-node consistency is handled through explicit message queue transfers. This segmentation allows each node to use simple coherent memory while the system as a large scale through the queue-based coordination layer.
3Productivity
If message queues are implemented in fabric memory accessible by all nodes, then data can be transferred across nodes, but unnecessary traffic is generated as nodes poll and access queues through the non-coherent fabric
Solution Approach 1:
The patent implements local quality by allowing each SMP node to have message queues located in its own local memory space. This means that when a node needs to access its own send or receive queues, the access is local and does not generate fabric traffic. Only the actual data transfers between nodes use the fabric, reducing unnecessary traffic.
4Productivity
If target locations for transferred data are not located within the coherence domain of the receiving node, then data can be stored remotely, but subsequent access requires additional coherence operations
Solution Approach 1:
The patent applies preliminary action by ensuring that when data is transferred between nodes, the target location is pre-selected to be within the coherence domain of the receiving node. This preliminary decision during the transfer phase ensures that subsequent accesses to the data can be served from the receiving node's local coherence domain without requiring additional coherence operations or fabric accesses.
Data Source
AI summary
Some examples described herein provide for a partially coherent memory transfer. An example method includes moving data directly from a coherence domain of an originating symmetric multiprocessor (SMP) node across a memory fabric to a target location for the data within a coherence domain of a receiving SMP node.