Partially Isolated FinFETs for Erosion Control
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Solution Overview
Problem
FinFET technology faces challenges such as fin erosion during gate and spacer etching, and epitaxial merge issues, which affect device performance and can cause source and drain shorts, particularly for the 14 nm node where trigate channel integration is complex.
Innovation Solution
A method for forming fin-shaped field effect transistors (FinFETs) with the channel on buried silicon oxide and source/drain on silicon, involving a well implant in the silicon substrate, forming vertical sources and drains through the buried oxide layer, and using dummy gates with a conformal spacer and hard mask layers to minimize fin erosion and ensure epitaxial merge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the thickness of fin hard mask is increased to minimize fin erosion, then fin erosion is reduced, but it is not friendly for trigate channel FinFET integration
Solution Approach 1:
The patent divides the FinFET structure into two distinct regions: channel fins on buried oxide and source/drain fins on silicon substrate. This segmentation allows different hard mask thicknesses to be used in different regions, with thicker hard mask in source/drain regions to prevent erosion and thinner hard mask in channel regions to enable trigate integration.
Solution Approach 2:
The patent applies different material properties and processing conditions to different parts of the device. Specifically, the channel portion uses buried oxide with controlled hard mask thickness for trigate compatibility, while the source/drain portions use silicon substrate with thicker hard mask to prevent fin erosion during etching processes.
2Productivity
If Fin epitaxial process is not well controlled, then source and drain short problem occurs at the gate line ends
Solution Approach 1:
The patent performs preliminary actions by forming the buried oxide layer and implanting wells in the silicon substrate before forming the fins. This preliminary preparation ensures that the epitaxial growth conditions are pre-established and controlled, preventing uncontrolled epitaxial merge that could cause source-drain shorts.
Solution Approach 2:
The buried oxide layer acts as an intermediary between the silicon substrate and the channel fins, providing a controlled interface that regulates epitaxial growth. This intermediary layer ensures consistent epitaxial merge while preventing direct uncontrolled interaction between source and drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fin erosion and ensures consistent epitaxial merge, enhancing FinFET device performance by maintaining structural integrity and preventing source and drain shorts, thus supporting reliable trigate channel integration.
Implementation Method 1
a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer
Implementation Method 2
implanting a well in the silicon substrate
Data Source
AI summary
A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates.