Partially Unrolled DFE Signaling Compression

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Solution Overview

Problem

The increasing number of PAM levels and taps in decision feedback equalizers (DFEs) leads to an exponential increase in the number of multiplexers needed for look-ahead and unrolling techniques, resulting in increased circuit area and power consumption.

Innovation Solution

Implementing a partially unrolled DFE that multiplexes only 2×1 bit symbols instead of 2×2 bit symbols, using a decompression circuit to transform the selected 1-bit output into a multi-bit sliced value by adding a pointer value associated with a PAM level region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of PAM levels and DFE taps are increased to improve signal processing capability, then the equalization performance is improved, but the number of multiplexers increases exponentially, resulting in increased circuit area and power consumption

Engineering Contradiction:
Improveequalization performanceVSAvoidnumber of multiplexers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the DFE operation into multiple stages: a compression stage that processes symbols through a reduced number of multiplexers, and a decompression stage that reconstructs the full-precision output. This segmentation allows the system to achieve high PAM level equalization performance while using fewer multiplexers during the critical processing stage.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the precision parameter of the signal representation by compressing multi-bit symbols to fewer bits during processing, then decompressing to the original precision. This parameter transformation allows the system to maintain equalization performance while reducing the complexity of the multiplexer network.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the number of PAM levels and DFE taps are increased to improve signal processing capability, then the equalization performance is improved, but the circuit area is increased due to more multiplexers and slicers

Engineering Contradiction:
Improveequalization performanceVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent segments the DFE architecture into a compression section with reduced multiplexer count and a decompression section. This segmentation enables the circuit to achieve the functionality of a high-PAM-level DFE with significantly fewer multiplexers and slicers, thereby reducing the overall circuit area while maintaining equalization performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a compressed representation of the symbol data that captures the essential information needed for equalization. This compressed copy is processed through the DFE, and then decompressed to produce the final output, reducing the need for full-precision multiplexers and slicers throughout the circuit.

Inventive Principle:
Principle #26Copying

3Reliability

If the number of PAM levels and DFE taps are increased to improve signal processing capability, then the equalization performance is improved, but the power consumption is increased due to more multiplexers

Engineering Contradiction:
Improveequalization performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent divides the DFE into compression and decompression stages, where the power-intensive multiplexer operations are concentrated in the compression stage with fewer multiplexers. The decompression stage uses simpler operations that consume less power, resulting in overall reduced power consumption while maintaining equalization performance for high PAM levels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the data precision parameter to reduce the number of active multiplexers during the most power-intensive processing stage. By processing compressed lower-precision data through the multiplexer network and only restoring full precision in the decompression stage, the system achieves high PAM equalization performance with significantly reduced power consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12294474B2Signaling compression and decompression associated with a partially unrolled decision feedback equalizer (DFE)
Publication Date: 2025.05.06 CADENCE DESIGN SYST INC
  • US12294474B2 patent drawing
  • US12294474B2 patent drawing
  • US12294474B2 patent drawing

AI summary

Technologies for signaling compression inside a partially unrolled decision feedback equalizer (DFE) are described. The signaling compression associated with partially unrolled DFE results in multiplexers selecting a 1-bit output value from one of two 1-bit input values, which are decoding the actual multi-bit candidate levels and transforming the selected 1-bit output value to a multi-bit sliced value by adding to it a pointer value of a pulse-amplitude modulation (PAM) level. The signaling compression reduces the power and area of an N-tap DFE, where N is a positive integer.