Inter-Partition Communication via Address Mapping

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Solution Overview

Problem

Multiprocessor computer systems face challenges in efficient communication between partitions due to logically distinct memory address spaces, which hinder seamless data transfer and coordination among nodes.

Innovation Solution

Assigning unique node numbers to nodes across partitions and implementing programmable address maps and routing tables to map memory address ranges and message buffers, enabling efficient inter-node communication while maintaining logical distinctness of memory address spaces.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If memory address spaces are kept logically distinct for each partition, then system modularity and independence are improved, but communication efficiency between partitions deteriorates

Engineering Contradiction:
Improvememory address space independenceVSAvoidcommunication efficiency
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent introduces a message buffer as an intermediary mechanism between partitions. The message buffer is mapped into the memory address space of each partition, allowing nodes to communicate by writing messages to buffers in other partitions. This intermediary structure enables efficient communication while preserving the logical independence of memory address spaces, as nodes communicate through the buffer rather than directly accessing each other's memory.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The communication mechanism is segmented into distinct components: message buffers, address maps, and routing tables. Each component has a specific function - message buffers hold data, address maps translate addresses between partitions, and routing tables direct messages to correct destinations. This segmentation allows each partition to maintain its address space independence while enabling coordinated communication through the segmented communication infrastructure.

Inventive Principle:
Principle #1Segmentation

2Speed

If direct memory access between partitions is enabled, then data transfer speed is improved, but system complexity and security risks increase

Engineering Contradiction:
Improvedata transfer speedVSAvoidsystem complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

Instead of enabling direct memory access between partitions, the patent uses message buffers as intermediaries. Nodes write messages to buffers in other partitions, and the buffer mechanism handles the actual data transfer. This approach achieves fast communication without requiring complex direct access paths, as the buffer abstraction simplifies the interaction model while maintaining speed through memory-based communication.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The message buffer mechanism is self-managing within each partition. Each partition has its own message buffers that are automatically mapped into its address space, and nodes within the partition can access these buffers using standard memory operations. This self-service approach reduces system complexity by eliminating the need for complex cross-partition memory management, as each partition independently manages its own buffers and address mappings.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS7882327B2Communicating between partitions in a statically partitioned multiprocessing system
Publication Date: 2011.02.01 ADVANCED MICRO DEVICES INC
  • US7882327B2 patent drawing
  • US7882327B2 patent drawing
  • US7882327B2 patent drawing

AI summary

In one embodiment, a method comprises assigning a unique node number to each of a first plurality of nodes in a first partition of a system and a second plurality of nodes in a second partition of the system. A first memory address space spans first memory included in the first partition and a second memory address space spans second memory included in the second partition. The first memory address space and the second memory address space are generally logically distinct. The method further comprises programming a first address map in the first partition to map the first memory address space to node numbers, wherein the programming comprises mapping a first memory address range within the first memory address space to a first node number assigned to a first node of the second plurality of nodes in the second partition, whereby the first memory address range is mapped to the second partition.