Partition-Aware Grid Graph for IC Routing
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Solution Overview
Problem
Conventional grid-based routing systems for integrated circuit design face challenges with unroutable regions and congestion, leading to design rule violations and inefficiencies due to their uniform grid representation.
Innovation Solution
The implementation of a non-uniform, partition-aware grid graph that aligns grid lines with partition boundaries, allowing for the removal of redundant lines, thereby reducing congestion and improving routing efficiency by enabling more precise routing paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform grid representation is used for routing, then the routing structure is simple and consistent, but it causes excessive memory usage and long computation time
Solution Approach 1:
The patent applies segmentation by dividing the uniform grid into multiple partitions based on circuit blocks. Each partition is processed independently, reducing the computational complexity and memory requirements for each routing operation while maintaining the overall routing structure.
Solution Approach 2:
The patent transforms the static uniform grid into a dynamic partition-aware grid where grid lines are selectively removed based on partition boundaries. This dynamic adaptation allows the routing structure to optimize itself for different routing scenarios, reducing unnecessary computation on already-routed or blocked regions.
2Ease of manufacture
If a uniform grid representation is used for routing, then the implementation is straightforward, but it leads to design rule violations due to congestion in unroutable regions
Solution Approach 1:
The patent applies local quality by making different regions of the grid have different properties. Grid lines are removed in specific locations where partitions exist, creating local variations in the routing structure that prevent congestion and design rule violations in those specific regions while maintaining uniformity in other areas.
Solution Approach 2:
The patent performs preliminary action by pre-removing grid lines that correspond to partition boundaries before the actual routing process begins. This prevents routers from attempting to route through unroutable regions, eliminating design rule violations before they can occur.
3Area of stationary object
If grid lines are retained in all regions, then complete coverage is achieved, but congestion occurs in unroutable regions leading to routing failures
Solution Approach 1:
The patent applies the extraction principle by removing unnecessary grid lines from regions that correspond to circuit partitions. This extraction eliminates congestion points and unroutable regions from the routing graph, allowing the router to focus only on valid routing paths and significantly improving routing success rate.
Data Source
AI summary
Aspects of the present disclosure address improved systems and methods of partition-aware grid graph based routing for integrated circuit designs. Consistent with some embodiments, a method may include accessing a design layout that defines a layout of components of an integrated circuit design, and includes one or more partitions. The method may further include building a uniform grid graph by superimposing a uniform grid structure over the design layout and inserting additional grid lines into the grid structure such that each partition boundary is aligned with a grid line. The method may further include removing redundant grid lines from the non-uniform grid graph resulting from inserting the additional grid lines, the result of which is the partition-aware grid graph. The method further includes using the partition-aware grid graph to route the integrated circuit design.