Partition-Based Formal Circuit Verification
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Solution Overview
Problem
Traditional formal analysis and verification of complex circuit designs become resource-intensive and inefficient due to their exhaustive nature, often resulting in ineffective verification operations, infinite loops, and degradation of results, especially when dealing with 'deep-state' properties that are not transparently accessible to designers.
Innovation Solution
The implementation of automatic deep-state formal circuit analysis tools that automate formal analysis operations by using default configuration values for non-exhaustive tools, generating diverse helper cover properties, filtering out unreachable covers, and maintaining analysis effectiveness through partitioning, monitoring, and regrouping to prevent resource wastage and stagnation, with features like stagnation detection and maximum time intervals for analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exhaustive formal analysis is used to verify complex circuit designs, then verification completeness is improved, but processing resources and time are excessively consumed
Solution Approach 1:
The circuit design is divided into multiple partitions or regions, and the verification process is segmented to focus on specific areas of interest rather than exhaustively analyzing the entire design. This allows verification of critical deep-state properties while reducing overall processing time and resource consumption.
Solution Approach 2:
Instead of performing complete exhaustive verification, the system applies partial verification actions targeting specific deep-state properties that are most critical or accessible. This non-exhaustive approach provides sufficient verification for important properties while avoiding the prohibitive cost of analyzing all possible states.
2Reliability
If exhaustive formal analysis is used to verify complex circuit designs, then verification completeness is improved, but processing resources are excessively consumed
Solution Approach 1:
The verification task is segmented into manageable partitions, allowing the system to allocate processing resources efficiently to specific regions or properties rather than uniformly consuming resources across the entire design. This reduces peak resource usage while maintaining verification effectiveness for critical areas.
Solution Approach 2:
The system performs partial verification actions focused on deep-state properties rather than exhaustive analysis of all circuit states. This reduces processing resource consumption by avoiding analysis of states that are either unreachable or less critical to the verification objectives.
3Reliability
If traditional formal verification tools are used, then comprehensive verification is achieved, but ineffective verification operations and infinite loops occur
Solution Approach 1:
The system incorporates feedback mechanisms that monitor the verification process for signs of stagnation or infinite loops. When verification operations fail to make progress or repeat patterns are detected, the system adjusts its strategy by changing partitions, modifying verification targets, or terminating unproductive operations, thereby improving overall verification efficiency.
Solution Approach 2:
The verification process is made dynamic by allowing the system to adapt its approach during execution. The tool can change verification targets, adjust partitioning strategies, and modify analysis depth based on runtime observations, enabling it to avoid infinite loops and focus on productive verification paths.
4Measurement precision
If deeper analysis of deep-state properties is performed, then verification accuracy is improved, but analysis complexity increases
Solution Approach 1:
The complex task of analyzing deep-state properties is segmented into smaller, more manageable verification targets. By dividing the analysis into discrete partitions and focusing on specific properties within each partition, the system achieves high verification accuracy for individual properties while keeping the complexity of each analysis step manageable.
Data Source
AI summary
Devices, methods, computer readable media, and other embodiments are described for automated formal analysis and verification of a circuit design. One embodiment involves accessing a circuit design and a set of default verification targets for the circuit design. A plurality of partitions for the circuit design are then automatically generated, and a first partition is analyzed to generate a first set of verification targets for the first partition based on the set of default verification targets and a set of partition and schedule values for the first partition. A first formal verification analysis is performed on the first partition, the first set of verification targets, and the set of partition and schedule values, and a formal verification output is generated based on the first formal verification analysis. Various embodiments can additionally involve stagnation analysis and additional automation to customize the analysis for each partition.