Partition-Based PLD Design Reuse to Reduce Processing Time
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Solution Overview
Problem
The existing processes for implementing user designs in programmable logic devices (PLDs) are resource-intensive, particularly during the mapping, placement, and routing steps, which become compounded as PLD sizes grow, leading to significant processing time and resource consumption when changes to the design are required, as most or all process steps need to be repeated.
Innovation Solution
A partition-based approach where the initial netlist is segmented into partitions, with each partition being mapped, placed, and routed, and the results stored for reuse when the design is revised, allowing unchanged partitions to skip re-processing, thereby reducing overall processing time and load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional full re-processing is used for design changes, then design optimization is maintained, but processing time and resource consumption increase significantly
Solution Approach 1:
The patent segments the PLD design into multiple independent partitions, allowing selective re-processing. When a design change occurs, only the affected partitions are identified and re-processed, while unchanged partitions retain their previously optimized results. This segmentation enables partial updates rather than full re-processing, significantly reducing processing time while maintaining optimization for changed portions.
Solution Approach 2:
The patent performs mapping, placement, and routing operations in advance for all partitions during the initial design phase. These preliminary results are stored and can be reused when design changes occur. By performing these intensive operations beforehand and caching the results, the system avoids redundant processing during subsequent design revisions, thus reducing processing time while preserving optimization quality.
2Reliability
If conventional full re-processing is used for design changes, then design correctness is maintained, but processing resources are consumed excessively
Solution Approach 1:
The patent divides the design into partitions and implements selective re-processing based on change detection. Only partitions that contain changed elements are re-processed, while unchanged partitions reuse their existing correct implementations. This segmentation approach maintains design correctness for all partitions while dramatically reducing the processing resources required compared to full re-processing.
Solution Approach 2:
The patent discards the approach of re-processing all partitions and instead recovers and reuses the mapping, placement, and routing results from unchanged partitions. By identifying which partitions remain unchanged and recovering their previously computed results, the system avoids wasting processing resources on redundant operations while maintaining design correctness.
3Adaptability or versatility
If PLD size increases, then functionality is enhanced, but processing complexity and resource requirements compound
Solution Approach 1:
The patent segments large PLD designs into multiple manageable partitions, making the processing complexity tractable even as PLD size and functionality increase. Each partition can be processed independently, and the segmentation allows the system to handle larger designs by dividing them into smaller units that can be managed separately and then integrated.
Solution Approach 2:
The patent introduces a new dimension of organization by dividing the PLD design into hierarchical partitions. This dimensional change from treating the design as a single monolithic unit to organizing it as a collection of independent partitions enables more efficient processing. The partitioning structure adds an organizational layer that reduces processing complexity while supporting enhanced functionality.
Data Source
AI summary
Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.