Partition Reset via Interrupt and Register Write
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Solution Overview
Problem
In multiple-partition computer systems, particularly those with Itanium Processor Family chips, resetting cells within a partition is challenging due to the need for individual reset of each partition and potential spurious errors from resource dependencies and timing issues.
Innovation Solution
A method involving firmware-executed reset code that builds a list of reset register addresses, sends interrupts to processors, and writes reset values to their registers, ensuring resources are managed coherently and dependencies are minimized, with the reset code executed from read-only memory to prevent errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cells are reset individually as they are located, then reset coherence is improved, but resources disappear that are still needed by other cells causing spurious errors
Solution Approach 1:
The patent applies preliminary action by collecting all necessary resources and building a complete list of reset register addresses before initiating the reset sequence. This ensures that all resources are secured and available before any cell reset begins, preventing the disappearance of needed resources during the reset process.
Solution Approach 2:
The patent introduces an intermediary mechanism in the form of a centralized reset management system that coordinates the reset process across multiple cells. This intermediary collects resources, manages the reset sequence, and ensures proper timing, acting as a mediator between the need for individual cell reset and the requirement to maintain resource availability.
2Ease of operation
If reset code is executed from main memory, then reset process is simplified, but main memory becomes incoherent as cells reset compromising the ability to complete the reset
Solution Approach 1:
The patent applies preliminary action by loading the reset code into read-only memory (ROM) in advance, before the reset process begins. This ensures the reset code is available in a stable, incoherent-free location that will not be affected by memory incoherence issues that arise during cell reset operations.
Solution Approach 2:
The patent uses read-only memory (ROM) as a disposable, non-volatile storage medium for the reset code. ROM provides a stable, immutable copy of the reset code that does not require coherence maintenance, serving as a reliable foundation for the reset process even when main memory becomes incoherent.
3Productivity
If cells are reset without attempting to idle the processors, then reset speed is improved, but CPU transactions depending on other resources introduce spurious errors
Solution Approach 1:
The patent applies preliminary action by sending interrupts to all processors before the reset begins, causing them to idle or complete their current transactions. This preliminary idling ensures that no transactions dependent on other resources are in progress when the reset starts, preventing spurious errors while maintaining fast reset execution.
Solution Approach 2:
The patent uses a coordinated interrupt mechanism that quickly transitions all processors to an idle state in parallel, then rapidly executes the reset sequence. This approach skips the lengthy process of individually stopping and idling each processor, achieving both speed and error prevention through synchronized action.
Data Source
AI summary
One embodiment of the invention is a method for resetting a partition of a multiple partition system, wherein the partition comprises a plurality of processors, the method comprising executing, by one processor of the plurality of processors, reset code from firmware, building a list of reset register addresses associated with the plurality of processors, sending an interrupt to the other processors of the plurality of processors, resetting the other processors by writing a reset code to their associated reset registers, and resetting the one processor by writing to its associated reset register.