Partition Wire Assignment for Multi-Partition Circuit Routing
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Solution Overview
Problem
Conventional CAD tools face challenges in generating high-quality partition wire assignments for multi-partition circuit designs in multi-die integrated circuits, often resulting in lower Quality of Result (QOR) and increased runtime, with many designs exceeding 99% SLL utilization becoming unroutable due to exponential search space explosion and inadequate handling of bottleneck problems.
Innovation Solution
A Computer-Aided Design (CAD) system that performs a global assignment phase by clustering super-long lines (SLLs) into bins and loads of nets into clusters, followed by a detailed assignment phase, using Integer Linear Programming (ILP) formulations to assign SLLs to nets while optimizing wirelength, congestion, and timing, significantly reducing runtime and improving QOR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CAD tools are used to route nets in multi-die ICs, then partition routing solutions can be generated, but the Quality of Result (QOR) is lower and runtime is significantly increased compared to monolithic die implementations
Solution Approach 1:
The patent segments the routing problem into two distinct phases: global assignment phase that determines which super-long lines (SLLs) are assigned to which nets, and detailed assignment phase that optimizes the specific wire assignments. This segmentation allows the complex routing problem to be solved more efficiently by breaking it into manageable stages, improving both QOR and reducing runtime compared to conventional single-phase approaches.
Solution Approach 2:
The patent performs preliminary clustering of SLLs into SLL bins and clustering of net loads into load clusters during the global assignment phase before detailed optimization. This preliminary organization of routing resources and net groups enables more efficient subsequent detailed assignment, avoiding the need to process all possible assignments from scratch and thereby reducing overall runtime while maintaining high QOR.
2Productivity
If available CAD tools are used for partition routing, then routing solutions can be generated, but extensive runtimes are required
Solution Approach 1:
By segmenting the routing workflow into global assignment and detailed assignment phases, the patent enables parallel processing and optimization at each stage. The global phase quickly assigns SLLs to nets using clustered representations, while the detailed phase refines assignments independently for each SLL bin, significantly improving routing throughput and reducing total runtime compared to conventional sequential tools.
Solution Approach 2:
The patent changes the representation parameters by clustering multiple SLLs into SLL bins and multiple net loads into load clusters, transforming the problem from individual wire assignments to group-level assignments. This parameter transformation reduces the search space complexity and enables faster convergence, thereby improving productivity while reducing runtime.
3Quantity of substance
If circuit designs utilize a significant percentage of available interposer wires, then high resource utilization is achieved, but the designs become unroutable due to exponential search space explosion
Solution Approach 1:
The patent fundamentally changes the problem parameters by introducing clustering: SLLs are grouped into SLL bins and net loads are grouped into load clusters. This transforms the assignment problem from matching individual SLLs to individual nets (which creates exponential search space at high utilization) to matching SLL bins to load clusters (which creates polynomial search space). This parameter transformation enables the routing of designs with very high SLL utilization (99%+) without exponential complexity explosion.
Solution Approach 2:
By segmenting both the SLL resources into bins and the net loads into clusters, the patent creates a hierarchical assignment structure that reduces search space complexity. The global phase assigns SLL bins to load clusters using reduced search space, and the detailed phase assigns individual SLLs within bins to individual nets within clusters. This two-level segmentation enables handling of high-utilization designs that would otherwise be unroutable.
Data Source
AI summary
Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.