Partitionable Data Bus for Faulty Bit Isolation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Die-stacked memory devices with high data connections are rendered faulty if a single bit is faulty, leading to lower manufacturing yield and higher costs due to the entire electronics package being considered 'dead' when a single bit in the 128-bit data bus fails.

Innovation Solution

A partitionable data bus system that allows for the isolation of faulty bits, enabling data transfer over a partitioned bus using additional cycles to compensate for data loss, allowing the system to remain operational even with faulty bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single bit in the 128-bit data bus is faulty, then the entire data bus is considered faulty, but this results in lower manufacturing yield and higher manufacturing cost

Engineering Contradiction:
Improvedata bus reliabilityVSAvoidmanufacturing yield
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The data bus is divided into multiple lanes, where each lane can independently transmit data. This segmentation allows the system to bypass faulty bits by switching to alternative lanes, thereby maintaining operational reliability while enabling the use of chips with minor defects, thus improving manufacturing yield.

Inventive Principle:
Principle #1Segmentation

2Reliability

If a single bit in the 128-bit data bus is faulty, then the entire electronics package is considered faulty, but this increases manufacturing cost

Engineering Contradiction:
Improveelectronics package reliabilityVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The data bus configuration is made dynamic through the ability to reconfigure which lanes are active based on detected faults. This dynamic adaptation allows the system to maintain reliability by activating only functional lanes, while avoiding the need to discard packages with minor defects, thereby reducing manufacturing costs.

Inventive Principle:
Principle #15Dynamics

3Reliability

If the entire data bus is considered faulty due to a single faulty bit, then data transfer cannot proceed, but this reduces productivity

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoiddata transfer efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the data bus into multiple independent lanes, the system can continue data transfer operations using functional lanes even when some bits are faulty. This maintains productivity by preventing complete data transfer failure, while ensuring reliability through the use of verified functional pathways.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9454419B2Partitionable data bus
Publication Date: 2016.09.27 ADVANCED MICRO DEVICES INC
  • US9454419B2 patent drawing
  • US9454419B2 patent drawing
  • US9454419B2 patent drawing

AI summary

A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.