Partitionable Decryption Engine for Power-Constrained AR Systems
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Solution Overview
Problem
Decryption operations in artificial reality systems, such as head-mounted displays, are computationally intensive and significantly impact performance and power consumption, leading to energy inefficiencies and potential decryption integrity issues.
Innovation Solution
The implementation of a reconfigurable decryption engine with a partitionable data path that allows selective enabling or disabling of encryption/decryption circuits, utilizing glitch-suppressing flip flops or latches to reduce power consumption by synchronizing asymmetric signal paths and operating at reduced frequencies, thereby reducing data interdependencies and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decryption operations are performed at full frequency to maintain decryption integrity, then decryption reliability is improved, but power consumption increases
Solution Approach 1:
The decryption engine dynamically adjusts its operating frequency based on the decryption mode. In full decryption mode, it operates at full frequency to ensure complete decryption of all frames. In sample decryption mode, it operates at reduced frequency (e.g., 1/4th or 1/8th) while maintaining decryption integrity for the selected subset of frames, thus resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The system performs partial decryption by selectively decrypting only a subset of frames (sample decryption mode) rather than all frames. This partial action reduces the overall computational load and power consumption while maintaining sufficient decryption integrity for the application's needs, balancing the contradiction between full decryption reliability and energy efficiency.
2Productivity
If all decryption circuits are enabled to process full decryption mode, then decryption speed is improved, but power consumption increases
Solution Approach 1:
The decryption engine is segmented into multiple independent decryption circuits (e.g., four circuits for processing four different frame sets). This segmentation allows selective enabling of only the necessary circuits based on the decryption mode. In sample decryption mode, only one or a subset of circuits are enabled, reducing power consumption while maintaining adequate decryption speed for the application.
Solution Approach 2:
The system dynamically configures the number of active decryption circuits based on the decryption mode. In full decryption mode, all circuits are enabled to maximize decryption speed. In sample decryption mode, fewer circuits are enabled at reduced frequency, optimizing the balance between decryption speed and power consumption for battery-powered devices.
3Reliability
If decryption is performed on all frames to ensure complete security, then security is improved, but processing time increases
Solution Approach 1:
The system performs partial decryption by selecting and decrypting only a subset of frames (e.g., every fourth or eighth frame) in sample decryption mode. This partial action maintains sufficient security for the application's needs while significantly reducing processing time and power consumption compared to decrypting all frames, thus resolving the contradiction between security and processing time.
4Use of energy by moving object
If decryption circuits operate at reduced frequency to save power, then power efficiency is improved, but decryption performance decreases
Solution Approach 1:
The decryption engine dynamically adjusts its operating frequency based on the decryption mode and system conditions. In full decryption mode, it operates at full frequency to maximize performance. In sample decryption mode, it operates at reduced frequency (e.g., 1/4th or 1/8th) which is sufficient for the reduced workload, thus achieving good power efficiency while maintaining adequate decryption performance for the application's needs.
Data Source
AI summary
In general, this disclosure describes scalable, partitionable encryption engines. The partitionable encryption engines of this disclosure yield power savings, such as by controlling operation of partitioned sub-datapaths at reduced clock rates. An apparatus includes an interface configured to receive a block of encrypted data for decryption, and a decryption engine in communication with the interface. The decryption engine includes a plurality of decryption sub-datapaths, where each respective decryption sub-datapath has no data interdependency with any other decryption sub-datapath of the plurality of decryption sub-datapaths. The decryption engine is configured to selectively enable one or more decryption sub-datapaths of the plurality of decryption sub-datapaths to decrypt the block of encrypted data to form a decrypted block of data.


