Partitionable Memory Interfaces for Parallel Data Transfer
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Solution Overview
Problem
Existing memory interface standards often result in over-fetching of data, wasting power and bandwidth due to minimum transaction sizes that exceed the actual data requirements, especially as data bus widths increase.
Innovation Solution
Implementing a method where multiple read and write commands are received and processed in parallel, with the data bus partitioned into portions to accommodate each command, allowing for reduced transaction sizes and efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory transactions are performed with minimum transaction sizes as specified by memory interface standards, then the interface compatibility is maintained, but over-fetching of data occurs which wastes power and bandwidth
Solution Approach 1:
The data bus is divided into multiple portions, with each portion handling data for a specific read or write command. This segmentation allows the memory device to transmit only the specific data requested by each command rather than transmitting minimum transaction sizes that exceed actual data requirements, thereby reducing power consumption and bandwidth waste while maintaining interface compatibility.
2Quantity of substance
If data bus width is increased to improve data transfer capacity, then bandwidth is improved, but over-fetching of data is exacerbated which increases power consumption
Solution Approach 1:
The increased data bus width is segmented into multiple portions, where each portion is allocated to handle data for a specific command. This allows the full bandwidth capacity to be utilized efficiently by transmitting only the exact amount of data needed for each command, preventing over-fetching even with wider buses, and thus maintaining high data transfer capacity without proportional increase in power consumption.
3Device complexity
If multiple read and write commands are processed serially, then command processing is simplified, but transaction size cannot be reduced leading to continued over-fetching
Solution Approach 1:
The data bus is segmented into multiple portions that can be simultaneously utilized for multiple commands. The memory device receives multiple read and write commands in parallel and assigns each command's data to a specific portion of the data bus. This segmentation enables reduced transaction sizes for each command while handling multiple commands concurrently, reducing power waste without significantly increasing processing complexity.
4Loss of energy
If multiple read and write commands are processed in parallel with data bus partitioning, then over-fetching is reduced and power is saved, but device complexity increases
Solution Approach 1:
The data bus is divided into multiple portions, with each portion dedicated to handling data for a specific command. This segmentation allows parallel processing of multiple commands with reduced transaction sizes, significantly reducing power consumption. The complexity increase is managed through systematic allocation of bus portions to commands, where the memory device maintains mapping between commands and their assigned bus portions, enabling efficient parallel processing without excessive complexity.
Data Source
AI summary
A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.